e4a7d9f693
The bus master bit is set at many places in coreboot's code, but the reason for that is not quite clear. We examined not setting the bus master bit whereever possible and tried booting without it, which worked fine for internal PCI devices but not for PCIe. As a PCIe device we used a Samsung M.2 NVMe SSD. For security reasons, we would like to disable bus mastering where possible. Depending on the device, bus mastering might get enabled by the operating system (e.g. for iGPU) and it might be required for some devices to work properly. However, the idea is to leave it disabled and configure the IOMMU first before enabling it. To have some sort of "backwards compatibility", add a method which configures bus mastering based on an additional config option. Since CB:42460 makes usage of this treewide, enable it by default to keep the current behaviour for now. Tested with Siemens/Chili, a Coffee Lake based platform. Change-Id: I876c48ea3fb4f9cf7b6a5c2dcaeda07ea36cbed3 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42459 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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| .. | ||
| dram | ||
| oprom | ||
| Kconfig | ||
| Makefile.inc | ||
| azalia_device.c | ||
| cardbus_device.c | ||
| cpu_device.c | ||
| device.c | ||
| device_const.c | ||
| device_util.c | ||
| hypertransport.c | ||
| i2c.c | ||
| i2c_bus.c | ||
| mmio.c | ||
| pci_class.c | ||
| pci_device.c | ||
| pci_early.c | ||
| pci_ops.c | ||
| pci_rom.c | ||
| pciexp_device.c | ||
| pcix_device.c | ||
| pnp_device.c | ||
| resource_allocator_common.c | ||
| resource_allocator_v3.c | ||
| resource_allocator_v4.c | ||
| root_device.c | ||
| smbus_ops.c | ||
| software_i2c.c | ||
| xhci.c | ||