Felix Held 8d0a609e6d soc,vendorcode/amd/cezanne: add basic FSP integration ... This is a trimmed-down version of the Cezanne FSP integration code, so for example the UPD definitions are empty, which will be addressed later. Since coreboot just leaves the UPD values at their default, this is not a problem during the initial platform bring-up. Change-Id: Ie0fc30120c2455aa2160708251e9d2f229984305 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>		2021-01-24 18:15:46 +00:00
..
amd	soc,vendorcode/amd/cezanne: add basic FSP integration	2021-01-24 18:15:46 +00:00
cavium	{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent	2020-09-01 03:06:04 +00:00
eltan	vc/eltan/security/verified_boot/vboot_check.c: Add check PROG_POSTCAR	2021-01-15 11:18:58 +00:00
google	vendorcode/google/chromeos: Build CSE Board Reset in Romstage	2021-01-22 22:53:07 +00:00
intel	{soc,vc,mb}/intel: Drop support for Cannon Lake SoC	2021-01-11 17:23:53 +00:00
siemens	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
Makefile.inc	…