coreboot-kgpe-d16/src
Daisuke Nojiri b0b4fd45e5 google/fizz: Configure GPP_C23 early
GPP_C23 is read by vboot_handoff to set the WP flag. Thus, it has
to be configured in early_gpio_table.

BUG=b:67030973
BRANCH=none
TEST=Verify by wpsw_boot and wpsw_cur match.

Change-Id: I96f2b53d7bc0901ffccce46b2d8ddae80c002fdc
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21876
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-04 23:13:44 +00:00
..
acpi src/acpi: Add guards on all header files 2017-08-01 23:04:27 +00:00
arch arch/riscv: hls_init: Initialize time{,cmp} with dummy pointers 2017-09-27 16:41:03 +00:00
commonlib commonlib: Consistently spell *romstage* without space 2017-09-27 22:20:25 +00:00
console console: Ignore loglevel in nvram until ramstage 2017-09-25 13:35:29 +00:00
cpu chromeec: Remove checks for EC in RO 2017-10-04 20:55:12 +00:00
device device/dram/ddr2.c: fix a hidden syntax error introduced earlier 2017-09-26 15:53:55 +00:00
drivers chromeec: Remove checks for EC in RO 2017-10-04 20:55:12 +00:00
ec chromeec: Remove checks for EC in RO 2017-10-04 20:55:12 +00:00
include cpu/amd/amdfam15: Add misc. SMM definitions 2017-09-27 15:57:16 +00:00
lib Kconfig: Move libhwbase related options into lib/Kconfig 2017-09-28 11:47:07 +00:00
mainboard google/fizz: Configure GPP_C23 early 2017-10-04 23:13:44 +00:00
northbridge nb/intel/gm45: Remove UMA alignment optimization 2017-10-03 19:48:01 +00:00
soc chromeec: Remove checks for EC in RO 2017-10-04 20:55:12 +00:00
southbridge smbus: Fix a typo ("Set the device I'm talking too") 2017-09-27 16:38:18 +00:00
superio winbond/w83627hf: Drop early_init.c 2017-09-21 15:40:49 +00:00
vboot chromeec: Remove checks for EC in RO 2017-10-04 20:55:12 +00:00
vendorcode intel/fsp: Update cannonlake FSP header 2017-10-04 02:55:29 +00:00
Kconfig Kconfig: Move libhwbase related options into lib/Kconfig 2017-09-28 11:47:07 +00:00