e3aeb93a52
recomendations.
Changes include the following:
fix > 4GB dqs tests
fix channel interleaving
ecc memory scrub updates
MC tristating updates
debug print changes
fix memory hoisting across nodes -
The DRAM Hole Address Register is set via devx in each node, but the Node
number <-> DRAM Base mapping and the Node number <-> DstNode mapping is
set in Node 0. The memmap is setup on node0 and copied to the other nodes
later. so dev, not devx. The bug was the hole was always being set on the
first node.
Signed-off-by: Marc Jones (marc.jones@amd.com)
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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| arch | ||
| boot | ||
| config | ||
| console | ||
| cpu | ||
| devices | ||
| drivers | ||
| include | ||
| lib | ||
| mainboard | ||
| northbridge | ||
| pc80 | ||
| pmc/altimus/mpc7410 | ||
| ram | ||
| sdram | ||
| southbridge | ||
| stream | ||
| superio | ||