coreboot-kgpe-d16/src
Patrick Rudolph b14b96d29a northbridge/intel/sandybridge/raminit: Prepare MRC path for x86_64
- Remove pointers in argument list passed to MRC to make sure the struct
  has the same size on x86_64 as on x86_32.
- Add assembly wrapper to call the MRC with argument in EAX.
- Wrap calling MRC in protected_mode_call_2arg, which is a stub on x86_32

Tested: Boots on Lenovo X220 using MRC in x86_32 and x86_64 mode.

Change-Id: Id755e7381c5a94360e3511c53432d68b7687df67
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-03 00:38:05 +00:00
..
acpi x86: Separate CPU and SoC physical address size 2023-12-22 12:26:59 +00:00
arch arch/x86/car.ld: Use VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE constant 2023-12-27 04:17:55 +00:00
commonlib commonlib/bsd: Tag CBMEM IDs deprecated for crashlog 2023-12-20 04:29:25 +00:00
console Allow to build romstage sources inside the bootblock 2023-11-09 13:20:18 +00:00
cpu Revert "cpu/intel/common: Define build time physical address reserved bits" 2023-12-22 12:26:42 +00:00
device x86: Separate CPU and SoC physical address size 2023-12-22 12:26:59 +00:00
drivers drivers/intel/gma: Only show the choice when a VBT is to be added 2023-12-26 17:41:36 +00:00
ec treewide: Use show_notices target for warnings 2023-12-20 04:06:55 +00:00
include sb/intel/bd82x6x: Add defines for PCI IDs 2023-12-23 19:58:44 +00:00
lib src/lib: Add memory/time saving special case for ramstage caching 2023-12-18 08:13:12 +00:00
mainboard mb/google/fizz: Make use of chipset devicetree 2024-01-02 11:56:27 +00:00
northbridge northbridge/intel/sandybridge/raminit: Prepare MRC path for x86_64 2024-01-03 00:38:05 +00:00
sbom sbom/Makefile.inc: Change GOPATH 2023-11-20 14:32:54 +00:00
security security/tpm: Retrieve factory configuration for device w/ Google TPM 2023-12-31 03:18:42 +00:00
soc soc/intel/meteorlake: Enable SSE2 accelerated RSA sign. verification 2024-01-02 03:40:18 +00:00
southbridge sb/intel/bd82x6x/pch: Add method to identify PCH 2023-12-26 17:03:56 +00:00
superio sio/nuvoton/npcd378: Fix ACPI errors 2023-12-16 22:58:35 +00:00
vendorcode vendorcode/google/chromeos: Add API for Chromebook Plus check 2023-12-31 03:19:54 +00:00
Kconfig Allow to build romstage sources inside the bootblock 2023-11-09 13:20:18 +00:00