Vladimir Serbinenko 4af1245ea1 intel/model_2065x: Remove dead code. ... nehalem uses gm45-like approach to resume backup so this code is never used. Change-Id: Ic32aa73f8d5b164b1c57815f6f44b2732fdbdcdb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5975 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>		2014-07-19 14:25:44 +02:00
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allwinner	src: Make use of 'CEIL_DIV(a, b)' macro across tree	2014-07-11 08:39:07 +02:00
amd	cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF	2014-07-17 02:20:12 +02:00
armltd	Introduce stage-specific architecture for coreboot	2014-05-06 20:23:31 +02:00
dmp	Introduce stage-specific architecture for coreboot	2014-05-06 20:23:31 +02:00
intel	intel/model_2065x: Remove dead code.	2014-07-19 14:25:44 +02:00
qemu-x86	Introduce stage-specific architecture for coreboot	2014-05-06 20:23:31 +02:00
samsung	src: Make use of 'CEIL_DIV(a, b)' macro across tree	2014-07-11 08:39:07 +02:00
ti	Introduce stage-specific architecture for coreboot	2014-05-06 20:23:31 +02:00
via	Drop redundant select CACHE_AS_RAM	2014-07-05 11:33:23 +02:00
x86	cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF	2014-07-17 02:20:12 +02:00
Kconfig	Move ARCH_* from board/Kconfig to cpu or soc Kconfig.	2014-05-03 00:25:20 +02:00
Makefile.inc	Introduce stage-specific architecture for coreboot	2014-05-06 20:23:31 +02:00