6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
99 lines
3.6 KiB
C
99 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* PCIe reset pin */
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#define GEN2_PCI_RESET_RESUMEWELL_GPIO 0
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static const struct reg_script gen2_gpio_init[] = {
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/* Initialize the legacy GPIO controller */
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGEN_CORE_WELL, 0x03),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGIO_CORE_WELL, 0x03),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGLVL_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTPE_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTNE_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGGPE_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGSMI_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTS_CORE_WELL, 0x03),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CNMIEN_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGEN_RESUME_WELL, 0x3f),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGIO_RESUME_WELL, 0x1c),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGLVL_RESUME_WELL, 0x02),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTPE_RESUME_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTNE_RESUME_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGGPE_RESUME_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGSMI_RESUME_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTS_RESUME_WELL, 0x3f),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RNMIEN_RESUME_WELL, 0x00),
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/* Initialize the GPIO controller */
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REG_GPIO_WRITE(GPIO_INTEN, 0),
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REG_GPIO_WRITE(GPIO_INTSTATUS, 0),
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REG_GPIO_WRITE(GPIO_SWPORTA_DR, 5),
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REG_GPIO_WRITE(GPIO_SWPORTA_DDR, 5),
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REG_GPIO_WRITE(GPIO_INTMASK, 0),
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REG_GPIO_WRITE(GPIO_INTTYPE_LEVEL, 0),
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REG_GPIO_WRITE(GPIO_INT_POLARITY, 0),
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REG_GPIO_WRITE(GPIO_DEBOUNCE, 0),
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REG_GPIO_WRITE(GPIO_LS_SYNC, 0),
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REG_SCRIPT_END
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};
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static const struct reg_script gen2_hsuart0[] = {
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/* Route UART0_TXD to MUX7_Y -> BUF_IO1 -> IO1 -> DIGITAL 1
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* Set MUX7_SEL (EXP1.P1_5) high
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* Configure MUX7_SEL (EXP1.P1_5) as an output
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* Set LVL_B_OE6_N (EXP0.P1_4) low
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* Configure LVL_B_OE6_N (EXP0.P1_4) as an output
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*/
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REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_OUTPUT1, BIT5),
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REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG1, ~BIT5),
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REG_I2C_AND(GEN2_I2C_GPIO_EXP0, GEN2_GPIO_EXP_OUTPUT1, ~BIT4),
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REG_I2C_AND(GEN2_I2C_GPIO_EXP0, GEN2_GPIO_EXP_CONFIG1, ~BIT4),
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/* Route DIGITAL 0 -> IO0 -> UART0_RXD
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* Set LVL_C_OE0_N (EXP1.P0_0) high
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* Configure LVL_C_OE0_N (EXP1.P0_0) as an output
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*/
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REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_OUTPUT0, BIT0),
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REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG0, ~BIT0),
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REG_SCRIPT_END
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};
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static const struct reg_script gen2_i2c_init[] = {
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/* Route I2C to Arduino Shield connector:
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* Set AMUX1_IN (EXP2.P1_4) low
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* Configure AMUX1_IN (EXP2.P1_4) as an output
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*
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* I2C_SDA -> ANALOG_A4
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* I2C_SCL -> ANALOG_A5
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*/
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REG_I2C_AND(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_OUTPUT1, ~BIT4),
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REG_I2C_AND(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_CONFIG1, ~BIT4),
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/* Set all GPIO expander pins connected to the Reset Button as inputs
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* Configure Reset Button(EXP1.P1_7) as an input
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* Disable pullup on Reset Button(EXP1.P1_7)
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* Configure Reset Button(EXP2.P1_7) as an input
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* Disable pullup on Reset Button(EXP2.P1_7)
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*/
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REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG1, BIT7),
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REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_PULL_UP_DOWN_EN1, ~BIT7),
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REG_I2C_OR(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_CONFIG1, BIT7),
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REG_I2C_AND(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_PULL_UP_DOWN_EN1, ~BIT7),
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REG_SCRIPT_END
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};
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static const struct reg_script gen2_tpm_reset[] = {
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/* Reset the TPM using SW_RESET_N_SHLD (EXP1 P1.7):
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* low, output, delay, input
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*/
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REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_OUTPUT1, ~BIT7),
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REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG1, ~BIT7),
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TIME_DELAY_USEC(5),
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REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG1, BIT7),
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REG_SCRIPT_END
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};
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