ae98e83eb2
Drop the implementation of statically allocated high memory region for CBMEM. There is no longer the need to explicitly select DYNAMIC_CBMEM, it is the only remaining choice. Change-Id: Iadf6f27a134e05daa1038646d0b4e0b8f9f0587a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7851 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
128 lines
2.8 KiB
Text
128 lines
2.8 KiB
Text
config SOC_NVIDIA_TEGRA124
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bool
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default n
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select ARCH_BOOTBLOCK_ARMV4
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select ARCH_VERSTAGE_ARMV4
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select ARCH_ROMSTAGE_ARMV7
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select ARCH_RAMSTAGE_ARMV7
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select HAVE_UART_SPECIAL
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select BOOTBLOCK_CONSOLE
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select ARM_BOOTBLOCK_CUSTOM
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select ARM_LPAE
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if SOC_NVIDIA_TEGRA124
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config BOOTBLOCK_CPU_INIT
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string
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default "soc/nvidia/tegra124/bootblock.c"
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help
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CPU/SoC-specific bootblock code. This is useful if the
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bootblock must load microcode or copy data from ROM before
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searching for the bootblock.
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# ROM image layout.
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#
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# 0x00000 Combined bootblock and BCT blob
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# 0x18000 Master CBFS header.
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# 0x18080 Free for CBFS data.
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#
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# iRAM (256k) layout.
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# (Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
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# so the bootblock loading address must be placed after that. After the
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# handoff that area may be reclaimed for other uses, e.g. CBFS cache.)
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#
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# 0x4000_0000 TTB (16K+32B). 32B is for L1 table of LPAE.
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# 0x4000_4020 CBFS mapping cache (96K-32B)
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# 0x4001_C000 Stack (16KB... don't reduce without comparing LZMA scratchpad!).
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# 0x4002_0000 Bootblock (max 48KB).
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# 0x4002_C000 ROM stage (max 80KB).
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# 0x4003_FFFF End of iRAM.
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config BOOTBLOCK_ROM_OFFSET
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hex
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default 0x0
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config CBFS_HEADER_ROM_OFFSET
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hex "offset of master CBFS header in ROM"
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default 0x1e000 if VBOOT2_VERIFY_FIRMWARE
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default 0x18000
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config CBFS_ROM_OFFSET
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hex "offset of CBFS data in ROM"
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default 0x1e080 if VBOOT2_VERIFY_FIRMWARE
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default 0x18080
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config SYS_SDRAM_BASE
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hex
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default 0x80000000
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config BOOTBLOCK_BASE
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hex
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default 0x40020000
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config ROMSTAGE_BASE
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hex
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default 0x4002d000 if VBOOT2_VERIFY_FIRMWARE
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default 0x4002c000
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config RAMSTAGE_BASE
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hex
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default 0x80200000
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config STACK_TOP
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hex
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default 0x40020000
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config STACK_BOTTOM
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hex
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default 0x4001c000
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# This is the ramstage thread stack, *not* the same as above! Currently unused.
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config STACK_SIZE
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hex
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default 0x800
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# TTB needs to be aligned to 16KB. Stick it in iRAM.
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config TTB_BUFFER
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hex "memory address of the TTB buffer"
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default 0x40000000
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config CBFS_CACHE_ADDRESS
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hex "memory address to put CBFS cache data"
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default 0x40004020
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config CBFS_CACHE_SIZE
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hex "size of CBFS cache data"
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default 0x00017fe0
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config VBOOT_WORK_BUFFER_ADDRESS
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hex "memory address of vboot work buffer"
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default 0x40018000
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config VBOOT_WORK_BUFFER_SIZE
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hex "size of vboot work buffer"
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default 0x00004000
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config TEGRA124_MODEL_TD570D
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bool "TD570D"
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config TEGRA124_MODEL_TD580D
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bool "TD580D"
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config TEGRA124_MODEL_CD570M
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bool "CD570M"
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config TEGRA124_MODEL_CD580M
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bool "CD580M"
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# Default to 2GHz, the lowest maximum frequency.
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config PLLX_KHZ
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int
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default 2000000 if TEGRA124_MODEL_TD570D
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default 2300000 if TEGRA124_MODEL_TD580D
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default 2100000 if TEGRA124_MODEL_CD570M
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default 2300000 if TEGRA124_MODEL_CD580M
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default 2000000
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endif
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