5a056d30a1
Panel datasheet defines some delay between PWM signal out and
backlight enable. This change fixes the current sequence
and makes the delays adjustable by dt setting.
BRANCH=none
BUG=chrome-os-partner:28008
TEST=Verified on Big DVT and Nyan/Norrin panels.
Panel works fine with dev mode, and the measurement
of power on sequence meets panel requirements.
Original-Change-Id: If6015bbb6015a3b203d425f5e90f676ad786b5e8
Original-Signed-off-by: Ken Chang <kenc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/196183
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 2bbcaa7281222ffc0b4026e8b1eb4c210a8e308a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id6424f66eb8dc6adeb70eaa33df742f4e57983c3
Reviewed-on: http://review.coreboot.org/7776
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
107 lines
3.1 KiB
C
107 lines
3.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __SOC_NVIDIA_TEGRA124_CHIP_H__
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#define __SOC_NVIDIA_TEGRA124_CHIP_H__
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#include <arch/cache.h>
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#include <soc/addressmap.h>
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#include "gpio.h"
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#define EFAULT 1
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#define EINVAL 2
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/* this is a misuse of the device tree. We're going to let it go for now but
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* we should at minimum have a struct for the display controller, since
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* the chip supports two.
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*/
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struct soc_nvidia_tegra124_config {
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u32 xres;
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u32 yres;
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u32 framebuffer_bits_per_pixel;
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u32 color_depth;
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u32 panel_bits_per_pixel;
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int cache_policy;
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/* there are two. It's not unimaginable that we might someday
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* have two of these structs in a single mainboard.
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*/
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u32 display_controller;
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u32 framebuffer_base;
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/* Technically, we can compute this. At the same time, some platforms
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* might want to specify a specific size for their own reasons. If it is
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* zero the soc code will compute it as xres*yres*framebuffer_bits_per_pixel/4
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*/
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u32 framebuffer_size;
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/* GPIOs -- all, some, or none are used. Unused ones can be ignored
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* in devicetree.cb since if they are not set there they default to 0,
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* and 0 for a gpio means 'unused GPIO'.
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*/
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gpio_t backlight_en_gpio;
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gpio_t lvds_shutdown_gpio;
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gpio_t backlight_vdd_gpio;
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gpio_t panel_vdd_gpio;
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/* required info. */
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/* pwm to use to set display contrast */
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int pwm;
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/* timings -- five numbers, all relative to the previous
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* event, not to absolute time. e.g., vdd_data_delay is the
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* delay from vdd on to data, not from power on to data.
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* This is stated to be four timings in the
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* u-boot docs. In any event, in coreboot, we generally
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* only delay long enough to let the panel wake up and then
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* do the control operations -- meaning, for *coreboot*
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* we probably only need the vdd_delay, but payloads may
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* need the other info.
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*/
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/* Delay before from power on asserting vdd */
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int vdd_delay_ms;
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/* Delay beween pwm and backlight_en_gpio is asserted */
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int pwm_to_bl_delay_ms;
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/* Delay before HPD high */
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int vdd_to_hpd_delay_ms;
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int hpd_unplug_min_us;
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int hpd_plug_min_us;
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int hpd_irq_min_us;
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int href_to_sync;
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int hsync_width;
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int hback_porch;
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int hfront_porch;
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int vref_to_sync;
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int vsync_width;
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int vback_porch;
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int vfront_porch;
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int pixel_clock;
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/* The minimum link configuraton settings */
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u32 lane_count;
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u32 enhanced_framing;
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u32 link_bw;
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u32 drive_current;
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u32 preemphasis;
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u32 postcursor;
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void *dc_data;
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};
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#endif /* __SOC_NVIDIA_TEGRA124_CHIP_H__ */
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