261226dd42
Change-Id: I4151d1a6ce94763432f307fbc8bc4afe229856ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
33 lines
721 B
C
33 lines
721 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <cpu/x86/smm.h>
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#include <device/device.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "onboard.h"
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void mainboard_suspend_resume(void)
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{
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/* Call SMM finalize() handlers before resume */
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apm_control(APM_CNT_FINALIZE);
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}
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static void mainboard_init(struct device *dev)
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{
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lan_init();
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}
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// mainboard_enable is executed as first thing after
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// enumerate_buses().
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static void mainboard_enable(struct device *dev)
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{
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dev->ops->init = mainboard_init;
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dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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