coreboot-kgpe-d16/src/northbridge
Timothy Pearson b474afdd21 nb/amd/mct_ddr3: Run fence training on each node after memory clock change
The BKDG requires phy fences to be re-trained after a memory clock change.
Memory training on the ASUS KGPE-D16 and KCMA-D8 somehow "mostly" worked
 -- without actually following this requirement -- !

Fix the single typo that caused several weeks of delay in putting
servers with Kingston RAM (and others) into production...

Tested-On: ASUS KGPE-D16
Config-CPU: 1x Opteron 6262HE
Config-RAM: 4x Crucial 36KSF1G72PZ-1G6M1
Change-Id: I197e6728d2b0ac8c1535740599459d080b17af33
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14445
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-22 17:29:01 +02:00
..
amd nb/amd/mct_ddr3: Run fence training on each node after memory clock change 2016-04-22 17:29:01 +02:00
dmp/vortex86ex tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
intel nb/intel/sandybridge/raminit: always use mrccache 2016-04-10 18:15:40 +02:00
rdc/r8610 tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
via kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ scheme 2016-04-19 18:34:18 +02:00