Subrata Banik d5be4e4046 soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi ... This patch creates a common instance of northbridge.asl inside intel common code (soc/intel/common/block/acpi/acpi) and changes cnl,icl & tgl soc code to refer northbridge.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify Device(MCHC) presence after booting to OS. Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38155 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-01-09 08:25:12 +00:00
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variants	mb/intel/coffeelake_rvp: Switch to overridetree setup	2019-12-05 21:25:33 +00:00
acpi_tables.c
board_info.txt
bootblock.c
chromeos.c	mb/*/chromeos.c: Remove some ENV_RAMSTAGE and __SIMPLE_DEVICE__	2019-07-25 16:03:37 +00:00
chromeos.fmd
chromeos_32MB.fmd
dsdt.asl	soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi	2020-01-09 08:25:12 +00:00
hda_verb.c
Kconfig	mb/intel/coffeelake_rvp: Switch to overridetree setup	2019-12-05 21:25:33 +00:00
Kconfig.name	src/mb/intel/coffeelake_rvp: Rename COMETLAKE_RVP to COMETLAKE_RVPU	2019-12-02 12:04:48 +00:00
mainboard.c
Makefile.inc
memory.c	soc/intel/cannonlake: Support different SPD read type for each slot	2019-05-15 17:47:13 +00:00
romstage.c	soc/intel/cannonlake: Support different SPD read type for each slot	2019-05-15 17:47:13 +00:00