4d5616bf40
TEST: same sha256sum with BUILD_TIMELESS=1. Change-Id: Icf3368bcf1351f0e7cd4041c3792d76362aec9e5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
67 lines
1.6 KiB
C
67 lines
1.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <baseboard/variants.h>
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#include <device/device.h>
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#include <nhlt.h>
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#include <soc/gpio.h>
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#include <soc/nhlt.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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static void mainboard_init(void *chip_info)
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{
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const struct pad_config *pads;
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size_t num;
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pads = variant_gpio_table(&num);
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gpio_configure_pads(pads, num);
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}
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static unsigned long mainboard_write_acpi_tables(struct device *device,
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unsigned long current,
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acpi_rsdp_t *rsdp)
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{
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uintptr_t start_addr;
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uintptr_t end_addr;
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struct nhlt *nhlt;
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start_addr = current;
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nhlt = nhlt_init();
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if (nhlt == NULL)
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return start_addr;
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variant_nhlt_init(nhlt);
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end_addr = nhlt_soc_serialize(nhlt, start_addr);
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if (end_addr != start_addr)
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acpi_add_table(rsdp, (void *)start_addr);
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return end_addr;
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}
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static void mainboard_enable(struct device *dev)
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{
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dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
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dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
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}
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struct chip_operations mainboard_ops = {
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.init = mainboard_init,
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.enable_dev = mainboard_enable,
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};
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