coreboot-kgpe-d16/src/cpu
Daniele Forsi b532b12b41 model_fxx/processor_name.c, hudson/lpc.c: add missing break statements
Found by Cppcheck 1.65. Fixes:
(warning) Variable 'processor_name_string' is reassigned a value before the old one has been used. 'break;' missing?
(warning) Variable 'rsize' is reassigned a value before the old one has been used. 'break;' missing?

Change-Id: I4a5c947fd5cc5797eb026475ec7036bc5eaf58db
Signed-off-by: Daniele Forsi <dforsi@gmail.com>
Reviewed-on: http://review.coreboot.org/6372
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-30 10:35:27 +02:00
..
allwinner src: Make use of 'CEIL_DIV(a, b)' macro across tree 2014-07-11 08:39:07 +02:00
amd model_fxx/processor_name.c, hudson/lpc.c: add missing break statements 2014-07-30 10:35:27 +02:00
armltd Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
dmp Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
intel cpu/intel/model_2065x/model_2065x_init.c: Remove dead code 2014-07-30 02:05:00 +02:00
qemu-x86 Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
samsung src: Make use of 'CEIL_DIV(a, b)' macro across tree 2014-07-11 08:39:07 +02:00
ti Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
via Drop redundant select CACHE_AS_RAM 2014-07-05 11:33:23 +02:00
x86 sandy/ivybridge: Native raminit. 2014-07-29 00:52:28 +02:00
Kconfig Move ARCH_* from board/Kconfig to cpu or soc Kconfig. 2014-05-03 00:25:20 +02:00
Makefile.inc Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00