Felix Singer 43b7f41678 src: Make PCI ID define names shorter ... Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>		2022-03-07 08:32:09 +00:00
..
g505s	mb/lenovo/g505s/acpi/ec.asl: Correct the path to "mainboard.h"	2022-02-22 21:25:25 +00:00
l520	sb/intel: Use bool for PCIe coalescing option	2022-01-04 11:48:19 +00:00
s230u	sb/intel: Use bool for PCIe coalescing option	2022-01-04 11:48:19 +00:00
t60	cpu/intel/speedstep: Constify get_cst_entries()	2021-10-19 15:00:01 +00:00
t400	cpu/intel/speedstep: Constify get_cst_entries()	2021-10-19 15:00:01 +00:00
t410
t420	sb/intel: Use bool for PCIe coalescing option	2022-01-04 11:48:19 +00:00
t420s	sb/intel: Use bool for PCIe coalescing option	2022-01-04 11:48:19 +00:00
t430	sb/intel: Use bool for PCIe coalescing option	2022-01-04 11:48:19 +00:00
t430s	sb/intel: Use bool for PCIe coalescing option	2022-01-04 11:48:19 +00:00
t440p	mainboard: Drop invalid VGA_BIOS_FILE defaults	2021-10-15 09:08:35 +00:00
t520	sb/intel: Use bool for PCIe coalescing option	2022-01-04 11:48:19 +00:00
t530	sb/intel: Use bool for PCIe coalescing option	2022-01-04 11:48:19 +00:00
thinkcentre_a58	cpu/intel/speedstep: Constify get_cst_entries()	2021-10-19 15:00:01 +00:00
w541
x1_carbon_gen1	sb/intel: Use bool for PCIe coalescing option	2022-01-04 11:48:19 +00:00
x60	src: Make PCI ID define names shorter	2022-03-07 08:32:09 +00:00
x131e	sb/intel: Use bool for PCIe coalescing option	2022-01-04 11:48:19 +00:00
x200	cpu/intel/speedstep: Constify get_cst_entries()	2021-10-19 15:00:01 +00:00
x201
x220	arch/x86: consolidate HPET base address definitions	2022-02-25 17:44:11 +00:00
x230	sb/intel: Use bool for PCIe coalescing option	2022-01-04 11:48:19 +00:00
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