b59980b54e
The Intel FSP provides a default set of IO-APIC IRQs for PCI devices, if the DevIntConfigPtr UPD is not filled in. However, the FSP has a list of rules that the input IRQ table must conform to: 1) One entry per slot/function 2) Functions using PIRQs must use IOxAPIC IRQs 16-23 3) Single-function devices must use INTA 4) Each slot must have consistent INTx<->PIRQy mappings 5) Some functions have special interrupt pin requirements 6) PCI Express RPs must be assigned in a special way (FIXED_INT_PIN) 7) Some functions require a unique IRQ number 8) PCI functions must avoid sharing an IRQ with a GPIO pad which routes its IRQ through IO-APIC. Since the FSP has no visibility into the actual GPIOs used on the board when GpioOverride is selected, IRQ conflicts can occur between PCI devices and GPIOs. This patch gives SoC code the ability to generate a table of PCI IRQs that will meet the BWG/FSP rules and also not conflict with GPIO IRQs. BUG=b:130217151, b:171580862, b:176858827 TEST=Boot with patch series on volteer, verify IO-APIC IRQs in `/proc/interrupts` match what is expected. No `GSI INT` or `could not derive routing` messages seen in `dmesg` output. Verified TPM, touchpad, touchscreen IRQs all function as expected. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0c22a08ce589fa80d0bb1e637422304a3af2045c Reviewed-on: https://review.coreboot.org/c/coreboot/+/49408 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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| alderlake | ||
| apollolake | ||
| baytrail | ||
| braswell | ||
| broadwell | ||
| cannonlake | ||
| common | ||
| denverton_ns | ||
| elkhartlake | ||
| icelake | ||
| jasperlake | ||
| quark | ||
| skylake | ||
| tigerlake | ||
| xeon_sp | ||
| Kconfig | ||