Johnny Lin c05aa26a1f xeon_sp/{cpx,skx}: Add config IFD_CHIPSET 'lbg' ... This is needed for ifdtool -p to detect CPX and SKX Lewisburg PCH as IFDv2. Change-Id: I21df9f700aedf131a38a776e76722bf918e6af84 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55746 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-06-28 04:12:18 +00:00
..
acpi	src: Drop "This file is part of the coreboot project" lines	2021-05-10 15:07:33 +00:00
cpx	xeon_sp/{cpx,skx}: Add config IFD_CHIPSET 'lbg'	2021-06-28 04:12:18 +00:00
include/soc	src/intel/xeon_sp: add hardware error support (HEST)	2021-06-04 12:38:32 +00:00
ras	src/intel/xeon_sp: add hardware error support (HEST)	2021-06-04 12:38:32 +00:00
skx	xeon_sp/{cpx,skx}: Add config IFD_CHIPSET 'lbg'	2021-06-28 04:12:18 +00:00
acpi.c
bootblock.c	security/intel/cbnt: Add logging	2021-06-21 05:42:00 +00:00
chip_common.c
finalize.c
gpio.c
Kconfig	cpu/x86: Default to PARALLEL_MP selected	2021-06-07 21:02:54 +00:00
lockdown.c
lpc.c	arch/x86/ioapic: Add get_ioapic_id() and get_ioapic_version()	2021-06-12 15:48:49 +00:00
Makefile.inc	src/intel/xeon_sp: add hardware error support (HEST)	2021-06-04 12:38:32 +00:00
memmap.c
nb_acpi.c	src/intel/xeon_sp: add hardware error support (HEST)	2021-06-04 12:38:32 +00:00
pch.c
pmc.c
pmutil.c
ramstage.c
reset.c
romstage.c
smihandler.c
smmrelocate.c
spi.c
uncore.c	soc/intel/xeon_sp: Skip locking down TXT related registers	2021-05-20 16:22:11 +00:00
util.c