4681b2778b
Set the SATA and SSATA REGLOCK as indicated by the Intel documentation. Change-Id: I90e6d0e3b5a38bcd5392e26cbbb6dc4aa6a8304b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
52 lines
1.3 KiB
C
52 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mmio.h>
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#include <device/pci.h>
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#include <intelblocks/cfg.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pmclib.h>
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#include <intelpch/lockdown.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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static void lpc_lockdown_config(int chipset_lockdown)
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{
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/* Set BIOS Interface Lock, BIOS Lock */
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if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
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lpc_set_bios_interface_lock_down();
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lpc_set_lock_enable();
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}
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}
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static void pmc_lockdown_config(int chipset_lockdown)
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{
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uint8_t *pmcbase;
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u32 pmsyncreg;
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/* PMSYNC */
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pmcbase = pmc_mmio_regs();
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pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
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pmsyncreg |= PMSYNC_LOCK;
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write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
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/* Make sure payload/OS can't trigger global reset */
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pmc_global_reset_disable_and_lock();
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/* Lock PMC stretch policy */
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pci_or_config32(PCH_DEV_PMC, GEN_PMCON_B, SLP_STR_POL_LOCK);
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}
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static void sata_lockdown_config(int chipset_lockdown)
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{
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if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
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pci_or_config32(PCH_DEV_SATA, SATAGC, SATAGC_REGLOCK);
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pci_or_config32(PCH_DEV_SSATA, SATAGC, SATAGC_REGLOCK);
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}
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}
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void soc_lockdown_config(int chipset_lockdown)
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{
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lpc_lockdown_config(chipset_lockdown);
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pmc_lockdown_config(chipset_lockdown);
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sata_lockdown_config(chipset_lockdown);
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}
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