coreboot-kgpe-d16/src/northbridge/intel/gm45
Nico Huber 58ba83fe74 nb/intel/gm45: Reserve MMIO and firmware memory below 1MiB
It looks like we didn't care to reserve the VGA MMIO (a & b segments)
and the c..f segments, initially. It was probably never needed until
the new resource allocator that will make use of any unclaimed space.

Change-Id: Iebdae64914d9f8301cafc67a5aba933c11294707
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-18 23:01:28 +00:00
..
acpi drivers/intel/gma: Include gfx.asl by default for all platforms... 2020-12-30 16:35:36 +00:00
acpi.c nb/intel/gm45: Deduplicate PCIEXBAR decoding 2020-08-04 12:23:04 +00:00
bootblock.c northbridge/intel/gm45/bootblock.c: Remove repeated word 2021-01-18 07:38:22 +00:00
chip.h
early_init.c nb/intel/gm45: Clean up header handling 2020-10-24 20:42:32 +00:00
early_reset.c nb/intel/gm45: Use PCI bitwise ops 2020-08-04 12:22:04 +00:00
gm45.h Revert "nb/intel/gm45/gm45.h: Remove duplicated include" 2021-01-18 09:40:00 +00:00
gma.c nb/intel/gm45: Use PCI bitwise ops 2020-08-04 12:22:04 +00:00
igd.c nb/intel/gm45: Use PCI bitwise ops 2020-08-04 12:22:04 +00:00
iommu.c nb/intel/gm45: Use PCI bitwise ops 2020-08-04 12:22:04 +00:00
Kconfig
Makefile.inc
memmap.c
memmap.h nb/intel/gm45: Introduce memmap.h 2020-10-24 20:42:19 +00:00
northbridge.c nb/intel/gm45: Reserve MMIO and firmware memory below 1MiB 2021-01-18 23:01:28 +00:00
pcie.c nb/intel/gm45: Clean up header handling 2020-10-24 20:42:32 +00:00
pm.c
raminit.c nb/intel/gm45: Add more DMIBAR/EPBAR registers 2020-10-24 20:42:07 +00:00
raminit_rcomp_calibration.c
raminit_read_write_training.c
raminit_receive_enable_calibration.c
romstage.c nb/intel/gm45: Use PCI bitwise ops 2020-08-04 12:22:04 +00:00
thermal.c