162 lines
5.4 KiB
Markdown
162 lines
5.4 KiB
Markdown
coreboot 4.14
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=============
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coreboot 4.14 was released on May 10th, 2021.
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Since 4.13 there have been 3660 new commits by 215 developers.
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Of these, about 50 contributed to coreboot for the first time.
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Welcome to the project!
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These changes have been all over the place, so that there's no
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particular area to focus on when describing this release: We had
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improvements to mainboards, to chipsets (including much welcomed
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work to open source implementations of what has been blobs before),
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to the overall architecture.
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Thank you to all developers who made coreboot the great open source
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firmware project that it is, and made our code better than ever.
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New mainboards
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--------------
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* AMD Bilby
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* AMD Majolica
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* GIGABYTE GA-D510UD
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* Google Blipper
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* Google Brya
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* Google Cherry
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* Google Collis
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* Google Copano
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* Google Cozmo
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* Google Cret
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* Google Drobit
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* Google Galtic
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* Google Gumboz
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* Google Guybrush
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* Google Herobrine
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* Google Homestar
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* Google Katsu
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* Google Kracko
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* Google Lalala
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* Google Makomo
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* Google Mancomb
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* Google Marzipan
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* Google Pirika
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* Google Sasuke
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* Google Sasukette
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* Google Spherion
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* Google Storo
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* Google Volet
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* HP 280 G2
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* Intel Alderlake-M RVP
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* Intel Alderlake-M RVP with Chrome EC
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* Intel Elkhartlake LPDDR4x CRB
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* Intel shadowmountain
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* Kontron COMe-mAL10
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* MSI H81M-P33 (MS-7817 v1.2)
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* Pine64 ROCKPro64
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* Purism Librem 14
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* System76 darp5
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* System76 galp3-c
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* System76 gaze15
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* System76 oryp5
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* System76 oryp6
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Removed mainboards
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------------------
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* Google Boldar
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* Intel Cannonlake U LPDDR4 RVP
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* Intel Cannonlake Y LPDDR4 RVP
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Deprecations and incompatible changes
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-------------------------------------
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### SAR support in VPD for Chrome OS
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SAR support in VPD has been deprecated for Chrome OS platforms for > 1
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year now. All new Chrome OS platforms have switched to using SAR
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tables from CBFS. For the next release, coreboot is updated to align
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with the Chrome OS factory changes and hence SAR support in VPD is
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deprecated in [CB:51483](https://review.coreboot.org/51483). Starting
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with this release, anyone building coreboot for an already released
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Chrome OS platform with SAR table in VPD will have to extract the
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"wifi_sar" key from VPD and add it as a file to CBFS using following
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steps:
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* On DUT, read SAR value using `vpd -i RO_VPD -g wifi_sar`
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* In coreboot repo, generate CBFS SAR file using:
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`echo ${SAR_STRING} > site-local/${BOARD}-sar.hex`
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* Add to site-local/Kconfig:
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```
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config WIFI_SAR_CBFS_FILEPATH
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string
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default "site-local/${BOARD}-sar.hex"
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```
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### CBFS stage file format change
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[CB:46484](https://review.coreboot.org/46484) changed the in-flash
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file format of coreboot stages to prepare for per-file signature
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verification. As described in the commit message in more details,
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when manipulating stages in a CBFS, the cbfstool build must match the
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coreboot image so that they're using the same format: coreboot.rom
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and cbfstool must be built from coreboot sources that either both
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contain this change or both do not contain this change.
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Since stages are usually only handled by the coreboot build system
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which builds its own cbfstool (and therefore it always matches
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coreboot.rom) this shouldn't be a concern in the vast majority of
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scenarios.
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Significant changes
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-------------------
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### AMD SoC cleanup and initial Cezanne APU support
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There's initial support for the AMD Cezanne APUs in the tree. This code
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hasn't started as a copy of the previous generation, but was based on a
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slightly modified version of the example/min86 SoC. During the cleanup
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of the existing Picasso SoC code the common parts of the code were
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moved to the common AMD SoC code, so that they could be used by the
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Cezanne code instead of adding another slightly different copy.
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### X86 bootblock layout
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The static size C_ENV_BOOTBLOCK_SIZE was mostly dropped in favor of
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dynamically allocating the stage size; the Kconfig is still available
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to use as a fixed size and to enforce a maximum for selected chipsets.
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Linker sections are now top-aligned for a reduced flash footprint and to
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maintain the requirements of near jump from reset vector.
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### ACPI GNVS framework
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SMI handlers for APM_CNT_GNVS_UDPATE were dropped; GNVS pointer to SMM is
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now passed from within SMM_MODULE_LOADER. Allocation and initialisations
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for common ACPI GNVS table entries were largely moved to one centralized
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implementation.
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### Intel Xeon Scalable Processor support is now considered mature
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Intel Xeon Scalable Processor (Xeon-SP) family [1] is designed
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primarily to serve the needs of the server market.
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coreboot support for Xeon-SP is in src/soc/intel/xeon_sp directory.
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This release has support for SkyLake-SP (SKX-SP) which is the 2nd
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generation, and for Cooper Lake-SP (CPX-SP) which is the 3rd generation
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or the latest generation [2] on market.
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With this release, the codebase for multiple generations of Xeon-SP
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were unified and optimized:
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* SKX-SP SoC code is used in OCP TiogaPass mainboard [3]. Support for
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this board is in Proof Of Concept Status.
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* CPX-SP SoC code is used in OCP DeltaLake mainboard. Support for
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this board is in DVT (Design Validation Test) exit equivalent status.
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Features supported, (performance/stability) test scopes, known issues,
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features gaps are described in [4].
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[1] https://www.intel.com/content/www/us/en/products/details/processors/xeon/scalable.html
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[2] https://www.intel.com/content/www/us/en/products/docs/processors/xeon/3rd-gen-xeon-scalable-processors-brief.html
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[3] ../mainboard/ocp/tiogapass.md
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[4] ../mainboard/ocp/deltalake.md
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