coreboot-kgpe-d16/src/arch/x86/include
Duncan Laurie b6e97b19ae Add support for storing POST codes in CMOS
This will use 3 bytes of CMOS to keep track of the POST
code for the current boot while also leaving a record of
the previous boot.

The active bank is switched early in the bootblock.

Test:
1) clear cmos
2) reboot
3) use "mosys nvram dump" to verify that the first byte
contains 0x80 and the second byte contains 0xF8
4) powerd_suspend and then resume
5) use "mosys nvram dump" to verify that the first byte
contains 0x81 and the second byte contains 0xFD

Change-Id: I1ee6bb2dac053018f3042ab5a0b26c435dbfd151
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1743
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08 19:40:40 +01:00
..
arch acpi: Add support for DMAR tables (Intel IOMMU support) 2012-11-06 22:25:29 +01:00
bitops.h
bootblock_common.h Add support for storing POST codes in CMOS 2012-11-08 19:40:40 +01:00
div64.h drop unused code in div64.h 2010-12-16 23:57:43 +00:00
stddef.h Make the device tree available in the rom stage 2012-08-04 18:05:39 +02:00
stdint.h