coreboot-kgpe-d16/src/include/pc80
Duncan Laurie b6e97b19ae Add support for storing POST codes in CMOS
This will use 3 bytes of CMOS to keep track of the POST
code for the current boot while also leaving a record of
the previous boot.

The active bank is switched early in the bootblock.

Test:
1) clear cmos
2) reboot
3) use "mosys nvram dump" to verify that the first byte
contains 0x80 and the second byte contains 0xF8
4) powerd_suspend and then resume
5) use "mosys nvram dump" to verify that the first byte
contains 0x81 and the second byte contains 0xFD

Change-Id: I1ee6bb2dac053018f3042ab5a0b26c435dbfd151
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1743
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08 19:40:40 +01:00
..
i8254.h Enable/fix compilation of i8254 code in ram stage. 2011-10-13 20:00:22 +02:00
i8259.h Rewrite interrupt handling in coreboot to be more comprehensible and 2009-07-21 21:36:41 +00:00
isa-dma.h
keyboard.h Remove nonsensical wrapper for function in 2010-02-23 20:31:37 +00:00
mc146818rtc.h Add support for storing POST codes in CMOS 2012-11-08 19:40:40 +01:00
tpm.h Add TPM support to coreboot 2012-03-30 02:04:20 +02:00
vga.h Various license header consistency fixes (trivial). 2010-02-15 23:10:19 +00:00
vga_io.h Various license header consistency fixes (trivial). 2010-02-15 23:10:19 +00:00