177 lines
6.3 KiB
Markdown
177 lines
6.3 KiB
Markdown
# ASRock H77 Pro4-M
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The ASRock H77 Pro4-M is a microATX-sized desktop board for Intel Sandy
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Bridge and Ivy Bridge CPUs.
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## Technology
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```eval_rst
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+------------------+--------------------------------------------------+
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| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
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+------------------+--------------------------------------------------+
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| Southbridge | Intel H77 (bd82x6x) |
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+------------------+--------------------------------------------------+
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| CPU socket | LGA 1155 |
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+------------------+--------------------------------------------------+
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| RAM | 4 x DDR3-1600 |
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+------------------+--------------------------------------------------+
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| Super I/O | Nuvoton NCT6776 |
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+------------------+--------------------------------------------------+
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| Audio | Realtek ALC892 |
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+------------------+--------------------------------------------------+
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| Network | Realtek RTL8111E |
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+------------------+--------------------------------------------------+
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| Serial | Internal header (RS-232) |
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+------------------+--------------------------------------------------+
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```
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## Status
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Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
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(linux-4.19.50).
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### Working
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- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120)
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- Native RAM initialization with four DIMMs
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- PS/2 combined port (mouse or keyboard)
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- Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub)
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- PCIe graphics in the PEG slot
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- All three additional PCIe slots
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- All rear and internal USB2 ports
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- All rear and internal USB3 ports
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- All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s)
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- All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s)
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- Rear eSATA connector (multiplexed with one ASM1061 port)
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- Gigabit Ethernet
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- Console output on the serial port
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- EDK II (MrChromebox's fork, at origin/uefipayload_202207) to boot
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Windows 10 (22H2) and Linux (5.19.17) via GRUB 2
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- SeaBIOS 1.16.1 to boot Windows 10 (needs VGA BIOS) and Linux via
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extlinux
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- Internal flashing with flashrom-1.2, see
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[Internal Programming](#internal-programming)
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- External flashing with flashrom-1.2 and a Raspberry Pi 1
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- S3 suspend/resume from either Linux or Windows 10
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- Poweroff
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### Not working
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- Booting from the two SATA ports provided by the ASM1061
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- Automatic fan control with the NCT6776D Super I/O
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### Untested
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- EHCI debug
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- S/PDIF audio
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- Other audio jacks than the green one, and the front panel header
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- Parallel port
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- Infrared/CIR
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- Wakeup from anything but the power button
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## Flashing coreboot
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```eval_rst
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+---------------------+------------+
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| Type | Value |
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+=====================+============+
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| Socketed flash | yes |
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+---------------------+------------+
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| Model | W25Q64.V |
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+---------------------+------------+
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| Size | 8 MiB |
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+---------------------+------------+
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| Package | DIP-8 |
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+---------------------+------------+
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| Write protection | no |
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+---------------------+------------+
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| Dual BIOS feature | no |
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+---------------------+------------+
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| Internal flashing | yes |
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+---------------------+------------+
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```
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The flash is divided into the following regions, as obtained with
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`ifdtool -f rom.layout backup.rom`:
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```
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00000000:00000fff fd
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00200000:007fffff bios
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00001000:001fffff me
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```
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### Internal programming
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The main SPI flash can be accessed using flashrom. By default, only
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the BIOS region of the flash is writable. If you wish to change any
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other region (Management Engine or flash descriptor), then an external
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programmer is required.
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The following command may be used to flash coreboot:
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```
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$ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom
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```
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The use of `--noverify-all` is required since the Management Engine
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region is not readable even by the host.
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```eval_rst
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In addition to the information here, please see the
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:doc:`../../tutorial/flashing_firmware/index`.
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```
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## Hardware monitoring and fan control
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There are two fan headers for the CPU cooler, CPU_FAN1 and CPU_FAN2. They share
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a single fan tachometer input on the Super I/O while some dedicated logic
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selects which one is allowed to reach it. Two GPIO pins on the Super I/O are
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used to control that logic. The firmware has to set them; coreboot selects
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CPU_FAN1 by default, but the user can change that setting if it was built with
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CONFIG_USE_OPTION_TABLE:
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```
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$ sudo nvramtool -e cpu_fan_header
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[..]
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$ sudo nvramtool -w cpu_fan_header=CPU_FAN2
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$ sudo nvramtool -w cpu_fan_header=None
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$ sudo nvramtool -w cpu_fan_header=Both
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```
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The setting will take effect after a reboot. Selecting and connecting both fan
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headers is possible but the Super I/O will report wrong fan speeds.
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Currently there is no automatic, OS-independent fan control, but a software
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like `fancontrol` from the lm-sensors package can be used instead.
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## Serial port header
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Serial port 1, provided by the Super I/O, is exposed on a pin header. The
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RS-232 signals are assigned to the header so that its pin numbers map directly
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to the pin numbers of a DE-9 connector. If your serial port doesn't seem to
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work, check if your bracket expects a different assignment. Also don't try to
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connect it directly to a device that operates at TTL levels - it would need a
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level converter like a MAX232.
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Here is a top view of the serial port header found on this board:
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+---+---+
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N/C | | 9 | RI -> pin 9
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+---+---+
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Pin 8 <- CTS | 8 | 7 | RTS -> pin 7
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+---+---+
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Pin 6 <- DSR | 6 | 5 | GND -> pin 5
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+---+---+
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Pin 4 <- DTR | 4 | 3 | TxD -> pin 3
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+---+---+
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Pin 2 <- RxD | 2 | 1 | DCD -> pin 1
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+---+---+
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## eSATA
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The eSATA port on the rear I/O panel and the internal connector SATA3_A1 share
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the same controller port on the ASM1061. Attaching an eSATA drive causes a
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multiplexer chip to disconnect the internal port from the SATA controller and
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connect the eSATA port instead. This can be seen on GP23 of the Super I/O
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GPIOs: it is '0' when something is connected to the eSATA port and '1'
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otherwise.
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