c5acd90b53
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
51 lines
1.1 KiB
Text
51 lines
1.1 KiB
Text
##
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## Config file for the Embedded Planet EP405PC Computing Engine
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##
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uses PCIC0_CFGADDR
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uses PCIC0_CFGDATA
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uses ISA_IO_BASE
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uses ISA_MEM_BASE
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uses TTYS0_BASE
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uses _IO_BASE
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##
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## Set PCI configuration register addresses
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##
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default PCIC0_CFGADDR=0xeec00000
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default PCIC0_CFGDATA=0xeec00004
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##
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## Set PCI/ISA I/O and memory base address
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##
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default ISA_IO_BASE=0xe8000000
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default ISA_MEM_BASE=0x80000000
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default _IO_BASE=ISA_IO_BASE
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##
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## HACK ALERT: the UART0 registers are not in the PCI I/O address space
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## but both IDE and UART use the same routines for I/O (inb/outb). To get
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## around this we set TTYSO_BASE to the difference between the two.
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##
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default TTYS0_BASE=0xef600300-ISA_IO_BASE
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##
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## Early board initialization, called from ppc_main()
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##
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initobject init.c
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driver pci_bridge.c
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arch ppc end
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cpu ppc/ppc4xx end
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##
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## Include the secondary Configuration files
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##
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southbridge winbond/w83c553 end
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##
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## Build the objects we have code for in this directory.
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##
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addaction linuxbios.a "$(CROSS_COMPILE)ranlib linuxbios.a"
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makedefine CFLAGS += -msoft-float
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