b82b4314ad
Looks like no one really knows what this bit would be useful for, nor when it would need to be set. Especially if coreboot is setting it even on PCI *Express* bridges. Digging through git history, nearly all instances of setting it on PCIe bridges comes from i82801gx, for which no reason was given as to why this would be needed. The other instances in Intel code seem to have been, unsurprisingly, copy-pasted. Drop all uses of this definition and rename it to avoid confusion. The negation in the name could trick people into setting this bit again. Tested on Asrock B85M Pro4, no visible difference. Change-Id: Ifaff29561769c111fb7897e95dbea842faec5df4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
139 lines
4.3 KiB
C
139 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/cardbus.h>
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/*
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* I don't think this code is quite correct but it is close.
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* Anyone with a cardbus bridge and a little time should be able
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* to make it usable quickly. -- Eric Biederman 24 March 2005
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*/
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/*
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* IO should be max 256 bytes. However, since we may have a P2P bridge below
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* a cardbus bridge, we need 4K.
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*/
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#define CARDBUS_IO_SIZE 4096
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#define CARDBUS_MEM_SIZE (32 * 1024 * 1024)
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static void cardbus_record_bridge_resource(struct device *dev, resource_t moving,
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resource_t min_size, unsigned int index, unsigned long type)
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{
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struct resource *resource;
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unsigned long gran;
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resource_t step;
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/* Initialize the constraints on the current bus. */
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resource = NULL;
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if (!moving)
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return;
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resource = new_resource(dev, index);
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resource->size = 0;
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gran = 0;
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step = 1;
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while ((moving & step) == 0) {
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gran += 1;
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step <<= 1;
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}
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resource->gran = gran;
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resource->align = gran;
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resource->limit = moving | (step - 1);
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resource->flags = type;
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/* Don't let the minimum size exceed what we can put in the resource. */
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if ((min_size - 1) > resource->limit)
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min_size = resource->limit + 1;
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resource->size = min_size;
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}
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void cardbus_read_resources(struct device *dev)
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{
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resource_t moving_base, moving_limit, moving;
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unsigned long type;
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u16 ctl;
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/* See if needs a card control registers base address. */
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pci_get_resource(dev, PCI_BASE_ADDRESS_0);
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compact_resources(dev);
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/* See which bridge I/O resources are implemented. */
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moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_0);
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moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_0);
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moving = moving_base & moving_limit;
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/* Initialize the I/O space constraints on the current bus. */
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cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE,
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PCI_CB_IO_BASE_0, IORESOURCE_IO);
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/* See which bridge I/O resources are implemented. */
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moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_1);
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moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_1);
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moving = moving_base & moving_limit;
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/* Initialize the I/O space constraints on the current bus. */
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cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE,
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PCI_CB_IO_BASE_1, IORESOURCE_IO);
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/* If I can, enable prefetch for mem0. */
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ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
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ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
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ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
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ctl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
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pci_write_config16(dev, PCI_CB_BRIDGE_CONTROL, ctl);
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ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
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/* See which bridge memory resources are implemented. */
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moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_0);
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moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_0);
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moving = moving_base & moving_limit;
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/* Initialize the memory space constraints on the current bus. */
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type = IORESOURCE_MEM;
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if (ctl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)
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type |= IORESOURCE_PREFETCH;
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cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE,
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PCI_CB_MEMORY_BASE_0, type);
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/* See which bridge memory resources are implemented. */
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moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_1);
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moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_1);
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moving = moving_base & moving_limit;
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/* Initialize the memory space constraints on the current bus. */
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cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE,
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PCI_CB_MEMORY_BASE_1, IORESOURCE_MEM);
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compact_resources(dev);
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}
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void cardbus_enable_resources(struct device *dev)
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{
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u16 ctrl;
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ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
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ctrl |= (dev->link_list->bridge_ctrl & (
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PCI_BRIDGE_CTL_VGA |
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PCI_BRIDGE_CTL_MASTER_ABORT |
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PCI_BRIDGE_CTL_BUS_RESET));
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/* Error check */
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ctrl |= (PCI_CB_BRIDGE_CTL_PARITY | PCI_CB_BRIDGE_CTL_SERR);
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printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
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pci_write_config16(dev, PCI_CB_BRIDGE_CONTROL, ctrl);
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pci_dev_enable_resources(dev);
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}
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struct device_operations default_cardbus_ops_bus = {
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.read_resources = cardbus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = cardbus_enable_resources,
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.scan_bus = pci_scan_bridge,
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.reset_bus = pci_bus_reset,
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};
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