4e9bb3308e
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
130 lines
2.9 KiB
Text
130 lines
2.9 KiB
Text
config SOC_INTEL_BRASWELL
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bool
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help
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Braswell M/D part support.
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if SOC_INTEL_BRASWELL
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select ARCH_X86
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select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
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select BOOT_DEVICE_SUPPORTS_WRITES
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select CACHE_MRC_SETTINGS
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select SUPPORT_CPU_UCODE_IN_CBFS
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select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
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select HAVE_SMI_HANDLER
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select PCIEXP_ASPM
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select PCIEXP_CLK_PM
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select PCIEXP_COMMON_CLOCK
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select PLATFORM_USES_FSP1_1
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select REG_SCRIPT
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select RTC
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_HDA
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select SOC_INTEL_COMMON_RESET
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select SPI_FLASH
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select SSE2
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select TSC_MONOTONIC_TIMER
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select TSC_SYNC_MFENCE
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select UDELAY_TSC
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select USE_GENERIC_FSP_CAR_INC
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT
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select HAVE_FSP_GOP
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select GENERIC_GPIO_LIB
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select INTEL_GMA_ACPI
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select INTEL_GMA_SWSMISCI
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select CPU_INTEL_COMMON
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select SOUTHBRIDGE_INTEL_COMMON_SMBUS
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select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
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select NO_CBFS_MCACHE
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x2000
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help
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The amount of anticipated stack usage in CAR by bootblock and
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other stages.
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config VBOOT
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select VBOOT_MUST_REQUEST_DISPLAY
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select VBOOT_STARTS_IN_ROMSTAGE
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config ECAM_MMCONF_BASE_ADDRESS
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default 0xe0000000
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config ECAM_MMCONF_BUS_NUMBER
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int
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default 256
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config MAX_CPUS
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int
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default 4
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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config SMM_RESERVED_SIZE
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hex
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default 0x100000
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# Cache As RAM region layout:
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#
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# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE
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# | Stack |
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# | | |
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# | v |
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# +-------------+
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# | ^ |
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# | | |
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# | CAR Globals |
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# +-------------+ DCACHE_RAM_BASE
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#
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config DCACHE_RAM_BASE
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hex
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default 0xfef00000
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
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must add up to a power of 2.
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config ENABLE_BUILTIN_COM1
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bool "Enable builtin COM1 Serial Port"
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default n
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help
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The PMC has a legacy COM1 serial port. Choose this option to
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configure the pads and enable it. This serial port can be used for
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the debug console.
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config DISABLE_HPET
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bool "Disable the HPET device"
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default n
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help
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Enable this to disable the HPET support
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Solves the Linux MP-BIOS bug timer not connected.
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config USE_GOOGLE_FSP
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bool
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help
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Select this to use Google's custom Braswell FSP header/binary
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instead of the public release on Github. Only google/cyan
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variants require this; all other boards should use the public release.
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config FSP_HEADER_PATH
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string
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default "\$(src)/vendorcode/intel/fsp/fsp1_1/braswell" if USE_GOOGLE_FSP
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default "3rdparty/fsp/BraswellFspBinPkg/Include/"
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help
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Location of FSP header file FspUpdVpd.h
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endif
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