134 lines
4.9 KiB
Markdown
134 lines
4.9 KiB
Markdown
# Facebook Monolith
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This page describes how to run coreboot on the Facebook Monolith.
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Please note: the coreboot implementation for this boards is in its
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Beta state and isn't fully tested yet.
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## Required blobs
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Mainboard is based on the Intel Kaby Lake U SoC.
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Intel company provides [Firmware Support Package (2.0)](../../soc/intel/fsp/index.md)
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(intel FSP 2.0) to initialize this generation silicon. Please see this
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[document](../../soc/intel/code_development_model/code_development_model.md).
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FSP Information:
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```eval_rst
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+-----------------------------+-------------------+-------------------+
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| FSP Project Name | Directory | Specification |
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+-----------------------------+-------------------+-------------------+
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| 7th Generation Intel® Core™ | KabylakeFspBinPkg | 2.0 |
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| processors and chipsets | | |
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| (formerly Kaby Lake) | | |
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+-----------------------------+-------------------+-------------------+
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```
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Microcode: 3rdparty/intel-microcode/intel-ucode
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## Flash components
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To create a complete flash image, the flash descriptor, GBE and ME blobs are required. The
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complete image can be used when e.g. a blank flash should be programmed. In other cases (when
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only coreboot needs to be replaced) placeholders can be used for the GBE and ME regions.
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These can be extracted from the original flash image as follows:
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1) Read the complete image from flash.
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2) Create a layout file with the following content:
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```
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00000000:00000fff fd
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00700000:00ffffff bios
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00003000:006FFFFF me
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00001000:00002fff gbe
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```
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3) Use `ifdtool -n <layout_file> <flash_image>` to resize the *bios* region from the default 6MB
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to 9 MB, this is required to create sufficient space for LinuxBoot.
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NOTE: Please make sure only the firmware descriptor (*fd*) region is changed. Older versions
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of the ifdtool corrupt the *me* region.
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4) Use `ifdtool -x <resized_flash_image>` to extract the components.
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The regions extracted can be used to generate a full flash image. The *bios* region is
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not needed as this is replaced by the coreboot image.
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NOTE: The gbe region contains the MAC address so be careful. When updating the flash using
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flashrom it is advisable to leave out the *gbe* area.
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## Flashing coreboot
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### Internal programming
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The SPI flash can be accessed using [flashrom].
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The descriptor area needs to be updated once to resize the *bios* region.
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`flashrom -p internal --ifd -i fd -w <coreboot.bin>`
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After that only the bios area should to be updated.
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`flashrom -p internal --ifd -i bios -w <coreboot.bin>`
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The *gbe* and *me* regions should not be updated.
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NOTE: As `flashrom --ifd` uses the flash descriptor it is required to update the
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descriptor and bios regions in the right sequence. Don't update both in one command.
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### External programming
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The system has an internal flash chip which is a 16 MiB soldered SOIC-8 chip.
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Specifically, it's a Winbond W25Q128JVSIQ (3.3V).
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The system has an external flash chip which is a 16 MiB soldered SOIC-8 chip.
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Specifically, it's a Winbond W25Q128JVSIM (3.3V).
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Flashing of these devices is very difficult, disassembling the system destroys the cooling
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solution. Wires need to be connected to be able to flash using an external programmer.
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## Known issues
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- None
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## Untested
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- Hardware monitor
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- Full Embedded Controller support
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- SATA
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- xDCI
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## Working
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- USB
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- Gigabit Ethernet (i219 and i210)
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- Graphics (Using FSP GOP)
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- flashrom
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- PCIe including hotplug on FPGA root port
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- EC serial port
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- EC CPU temperature
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- SMBus
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- Initialization with FSP
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- SeaBIOS payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4)
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- TianoCore payload (commit 860a8d95c2ee89c9916d6e11230f246afa1cd629)
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- LinuxBoot (kernel kernel-4_19_97) (uroot commit 9c9db9dbd6b532f5f91a511a0de885c6562aadd7)
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- eMMC
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All of the above has been briefly tested by booting Linux from eMMC using the TianoCore payload
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and LinuxBoot.
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SeaBios has been checked to the extend that it runs to the boot selection and provides display
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output.
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## Technology
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```eval_rst
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+------------------+--------------------------------------------------+
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| SoC | Intel Kaby Lake U |
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+------------------+--------------------------------------------------+
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| CPU | Intel i3-7100U |
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+------------------+--------------------------------------------------+
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| Super I/O, EC | ITE8528 |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel Management Engine |
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+------------------+--------------------------------------------------+
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```
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[W25Q128JVSIQ]: https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf
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[W25Q128JVSIM]: https://www.winbond.com/resource-files/w25q128jv%20dtr%20revb%2011042016.pdf
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[flashrom]: https://flashrom.org/Flashrom
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