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Patrick Rudolph b97009ed43 nb/intel/sandybridge/raminit: Fill SMBIOS type17 info
Fill minimal info required for SMBIOS type 17.
Report
 * DIMM size
 * channel
 * rank per DIMM
 * speed in Mhz
 * DIMM type
 * slot
 * manufacturer ID
 * serial

Allows dmidecode to print the current RAM configuration.

Test system:
 * Gigabyte GA-B75M-D3H
 * Intel Pentium CPU G2130
 * Linux 4.3
 * dmidecode 3.0

dmidecode output:
Handle 0x0005, DMI type 17, 40 bytes
Memory Device
	Array Handle: 0x0000
	Error Information Handle: Not Provided
	Total Width: 16 bits
	Data Width: 8 bits
	Size: 8192 MB
	Form Factor: DIMM
	Set: None
	Locator: Channel-0-DIMM-0
	Bank Locator: BANK 0
	Type: DDR3
	Type Detail: Synchronous
	Speed: 1600 MHz
	Manufacturer: Unknown (cd04)
	Serial Number: None
	Asset Tag: Not Specified
	Part Number: F3-1866C9-8GSR
	Rank: 2
	Configured Clock Speed: 1600 MHz
	Minimum Voltage: Unknown
	Maximum Voltage: Unknown
	Configured Voltage: Unknown

Handle 0x0006, DMI type 17, 40 bytes
Memory Device
	Array Handle: 0x0000
	Error Information Handle: Not Provided
	Total Width: 16 bits
	Data Width: 8 bits
	Size: 8192 MB
	Form Factor: DIMM
	Set: None
	Locator: Channel-1-DIMM-1
	Bank Locator: BANK 0
	Type: DDR3
	Type Detail: Synchronous
	Speed: 1600 MHz
	Manufacturer: Unknown (cd04)
	Serial Number: None
	Asset Tag: Not Specified
	Part Number: F3-1866C9-8GSR
	Rank: 2
	Configured Clock Speed: 1600 MHz
	Minimum Voltage: Unknown
	Maximum Voltage: Unknown
	Configured Voltage: Unknown

Change-Id: I4e5f772d68484b9cb178ca8a1d63ad99839f3993
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13852
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-03 20:42:11 +01:00
3rdparty vboot: Update to current master to support S3 resume signalling 2016-02-29 20:19:06 +01:00
Documentation Documentation/Intel: More CorebootPayloadPkg documentation 2016-02-29 04:59:26 +01:00
payloads coreinfo: quote $(AS) and $(CC) in $(LPAS) and $(LPCC) 2016-02-28 20:09:38 +01:00
src nb/intel/sandybridge/raminit: Fill SMBIOS type17 info 2016-03-03 20:42:11 +01:00
util amdfwtool: Fix some PSP2 issues 2016-03-03 12:03:03 +01:00
.clang-format Provide coreboot coding style formalisation file for clang-format 2015-11-10 00:49:03 +01:00
.gitignore Payloads: Add U-Boot as a coreboot-payload 2016-02-18 20:53:42 +01:00
.gitmodules git modules: rename git submodules to avoid hierarchies 2016-02-11 20:55:55 +01:00
.gitreview
COPYING
MAINTAINERS MAINTAINERS: Designate Intel maintainers for FSP 1.0 Baytrail 2015-12-30 20:06:52 +01:00
Makefile build system: avoid setting HOSTCC to " gcc" 2016-02-02 14:35:11 +01:00
Makefile.inc Makefile.inc: Add dependency on util/kconfig/conf for config.h 2016-03-01 20:48:53 +01:00
README README: improve description of compiler requirements 2015-07-30 05:11:33 +02:00
toolchain.inc power8: try to fix toolchain.inc for power8. 2016-02-17 23:43:38 +01:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.