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Furquan Shaikh b9c22e0965 util/sconfig: Compare probe conditions for override device match
When the override functionality looks for device match, check that
the probe list for both the devices matches exactly if probe list
exists for the base device. This ensures that if there are two devices
with same identity (e.g. I2C address or USB port #) but using
different properties (registers) controlled by different probe
statements, then the two devices are not incorrectly matched as the
same device.

The check for base device having a probe list is performed before
comparing the probe lists because a base device might not really have
any probe requirements at all. So, when overriding such a device,
there is no need to check for the probe list match.

BUG=b:187193527
TEST=Verified by adding two I2C devices in the override tree with the
same I2C address and chip but different probe statements and confirmed
that both the devices are present in generated static.c file.

Change-Id: Ib18868b336cf4ffc9aa38aee7c6f333a35d32fce
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-01 19:20:05 +00:00
3rdparty 3rdparty/intel-microcode: Update submodule to 20210608 release 2021-08-13 18:06:50 +00:00
Documentation Doc/mb/ocp: Add hyperlink to src/mainboard/ocp/deltalake/vpd.h 2021-09-01 15:22:05 +00:00
LICENSES treewide: Remove trailing whitespace 2021-02-17 17:30:05 +00:00
configs AGESA f15tn: Fix building IDS tracing support 2021-08-22 22:17:32 +00:00
payloads libpayload: cbgfx: Clear screen by sequential access 2021-08-27 02:53:38 +00:00
src mb/google/volteer: Move hda device enabling to override tree 2021-09-01 19:19:53 +00:00
tests tests: Fix function mocking for clang 2021-08-25 20:54:16 +00:00
util util/sconfig: Compare probe conditions for override device match 2021-09-01 19:20:05 +00:00
.checkpatch.conf lint: checkpatch: Only exclude specific src/vendorcode/ subdirectories 2021-04-06 16:04:41 +00:00
.clang-format lint/clang-format: set to 96 chars per line 2019-06-13 20:14:00 +00:00
.editorconfig Add .editorconfig file 2019-09-10 12:52:18 +00:00
.gitignore .gitignore: Ignore .test/.dependencies globally 2020-10-31 18:21:36 +00:00
.gitmodules .gitmodules: Update intel-microcode submodule to track branch=main 2021-06-09 17:20:50 +00:00
.gitreview
AUTHORS AUTHORS, util/: Drop individual copyright notices 2020-05-09 21:21:32 +00:00
COPYING
MAINTAINERS MAINTAINERS: add AMD Stoneyridge SoC 2021-08-17 17:10:22 +00:00
Makefile util/kconfig: Uprev to Linux 5.13's kconfig 2021-07-13 20:28:14 +00:00
Makefile.inc build system: Deduplicate symbols in objdump 2021-07-23 15:06:56 +00:00
README.md README.md: Remove link to deprecated wiki 2019-11-16 20:39:55 +00:00
gnat.adc treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
toolchain.inc toolchain.inc: copy architecture specific CFLAGS to GCC_ADAFLAGS 2021-07-01 09:43:54 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.