coreboot-kgpe-d16/src/soc/intel
Duncan Laurie 35dc00f75b broadwell: Preserve VbNv around cmos_init
To ensure that boot flags (legacy, usb, signed-only) are
properly restored from CMOS and used in the first boot after
a battery removal or RTC reset then the VbNv region needs to
be preserved around the cmos_init call.

When using vboot firmware selection and VbNv is stored in CMOS
then that region of CMOS will have been re-initialized by the
time we call cmos_init and reset CMOS if the chipset flag was
set indicating a problem.

BUG=chrome-os-partner:35240
BRANCH=broadwell
TEST=manual testing on samus:
1) boot in dev mode, enable dev_boot_legacy and ensure it works
2) on EC console pulse PCH_RTCRST_L low for a second
3) ensure first boot after RTC reset will still boot legacy mode
4) remove battery for a time
5) ensure first boot after battery is re-inserted will still
boot legacy mode

Change-Id: Ica256bbdcba6d4616957ff38e63914dd15f645c6
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 881c7841c95dec392a66eef38a7112c1f385fdfa
Original-Change-Id: I4c33f183ba4b301d68ae31c41fc6663f3be857b0
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241529
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9495
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10 20:16:59 +02:00
..
baytrail baytrail: fix the coding error on PCIe L1 exit latency 2015-04-10 20:06:59 +02:00
broadwell broadwell: Preserve VbNv around cmos_init 2015-04-10 20:16:59 +02:00
common baytrail: Fix hdmi audio choppy issue 2015-04-06 19:06:37 +02:00
fsp_baytrail build system: rename __BOOT_BLOCK__ and __VER_STAGE__ 2015-04-04 20:07:18 +02:00
Makefile.inc broadwell: Hook into the build system 2014-12-31 21:23:09 +01:00