Martin Roth bb27316264 fsp_baytrail: Update microcode for Gold 3 FSP release ... New microcode for Bay Trail I B2/B3 and D0 parts was released in the Gold 3 Bay Trail FSP release. Change the microcode size to an area instead of the exact size of the patches. This will hopefully reduce updates to the microcode size. Change-Id: I58b4c57a4bb0e478ffd28bd74a5de6bb61540dfe Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7647 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>		2014-12-05 21:40:25 +01:00
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intel	fsp_baytrail: Update microcode for Gold 3 FSP release	2014-12-05 21:40:25 +01:00
nvidia	Replace hlt with halt()	2014-12-02 10:25:55 +01:00
qualcomm	ipq8064: Make clock code build in coreboot	2014-12-05 20:22:55 +01:00
samsung	Replace hlt with halt()	2014-12-02 10:25:55 +01:00
ucb	Add UCB RISCV support for architecture, soc, and emulation mainboard..	2014-12-01 19:06:43 +01:00
Kconfig	Add UCB RISCV support for architecture, soc, and emulation mainboard..	2014-12-01 19:06:43 +01:00
Makefile.inc	Add UCB RISCV support for architecture, soc, and emulation mainboard..	2014-12-01 19:06:43 +01:00