03784fa97a
This patch adds a new static assertion macro that can be used to check the offsets in structures that overlay register sets at compile time. It uses the _Static_assert() declaration from the new ISO C11 standard, which is supported (even without -std=c11) by GCC after version 4.6. (There is supposedly also support in clang, although I haven't tried it... let's deal with compiler issues when/if they turn up.) I've added it to all structures for our current ARM SoCs for now, and I think every new register overlay we add going forward should use them (at least for the last member, but feel free to add more if you think it's useful). Change-Id: If32510e7049739ad05618d363a854dc372d64386 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179412 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit cef5fa13c31375a316ca4556c0039b17c8ea7900) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6905 Tested-by: build bot (Jenkins)
123 lines
2.6 KiB
C
123 lines
2.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __SOC_NVIDIA_TEGRA_USB_H__
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#define __SOC_NVIDIA_TEGRA_USB_H__
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#include <stdint.h>
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struct utmip_ctlr {
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u32 pll0;
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u32 pll1;
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u32 xcvr0;
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u32 bias0;
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u32 hsrx0;
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u32 hsrx1;
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u32 fslsrx0;
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u32 fslsrx1;
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u32 tx;
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u32 misc0;
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u32 misc1;
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u32 debounce;
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u32 batchrgr;
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u32 spare;
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u32 xcvr1;
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u32 bias1;
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u32 bias_sts;
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u32 chrgr_debounce;
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u32 misc_sts;
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u32 pmc_wakeup;
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};
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check_member(utmip_ctlr, pmc_wakeup, 0x84c - 0x800);
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struct usb_ctlr {
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u32 id;
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u32 _rsv0;
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u32 host;
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u32 device;
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u32 txbuf; /* 0x010 */
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u32 rxbuf;
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u32 _rsv1[58];
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u16 ehci_caplen; /* 0x100 */
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u16 ehci_version;
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u32 ehci_hcsp;
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u32 ehci_hccp;
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u32 _rsv2[5];
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u32 dci_version; /* 0x120 */
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u32 dcc_params;
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u32 extsts;
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u32 extintr;
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u32 ehci_usbcmd; /* 0x130 */
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u32 ehci_usbsts;
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u32 ehci_usbintr;
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u32 ehci_frindex;
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u32 _rsv3; /* 0x140 */
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u32 ehci_periodic_base;
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u32 ehci_async_base;
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u32 async_ttsts;
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u32 burst_size; /* 0x150 */
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u32 tx_fill_tuning;
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u32 _rsv4;
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u32 icusb_ctrl;
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u32 ulpi_viewport; /* 0x160 */
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u32 _rsv5[4];
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u32 ehci_portsc;
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u32 _rsv6[15];
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u32 lpm_ctrl;
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u32 _rsv7[15];
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u32 otgsc;
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u32 usb_mode;
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u32 _rsv8;
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u32 ep_nak; /* 0x200 */
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u32 ep_nak_enable;
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u32 ep_setup;
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u32 ep_init;
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u32 ep_deinit;
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u32 ep_sts;
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u32 ep_complete;
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u32 ep_ctrl[16];
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u32 _rsv9[105];
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u32 suspend_ctrl; /* 0x400 */
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u32 vbus_sensors;
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u32 vbus_wakeup_id;
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u32 alt_vbus_sts;
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u32 legacy_ctrl;
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u32 _rsv10[3];
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u32 interpacket_delay;
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u32 _rsv11[27];
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u32 resume_delay;
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u32 _rsv12;
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u32 spare;
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u32 _rsv13[9];
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u32 new_ctrl;
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u32 _rsv14[207];
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struct utmip_ctlr utmip; /* 0x800 */
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};
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check_member(usb_ctlr, utmip, 0x800);
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enum usb_phy_type { /* For use in lpm_ctrl[31:29] */
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USB_PHY_UTMIP = 0,
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USB_PHY_ULPI = 2,
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USB_PHY_ICUSB_SER = 3,
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USB_PHY_HSIC = 4,
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};
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void usb_setup_utmip(struct usb_ctlr *usb);
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void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type);
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#endif
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