John Zhao f3a8bf13cb soc/intel/alderlake: Drop 100ms delay and do not poll Link Active ... Drop the 100ms delay in the _PS0 method because kernel already adds this 100ms. This change also drops polling TBT PCIe root ports Link Active State because this scheme is not applicable for SW CM. BUG=None TEST=Built Alderlake coreboot image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I792d3c8ca4249ed74d4090ec1efba5a180429c75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51191 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-03-15 06:30:52 +00:00
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alderlake	soc/intel/alderlake: Drop 100ms delay and do not poll Link Active	2021-03-15 06:30:52 +00:00
apollolake	soc/intel/*: drop UART pad configuration from common code	2021-03-12 08:48:03 +00:00
baytrail	soc/intel/baytrail: Use cbmem_recovery()	2021-02-23 02:35:08 +00:00
braswell	soc/intel/braswell: Factor out common acpi_fill_madt	2021-03-12 15:41:35 +00:00
broadwell	pciexp_device: Rewrite LTR configuration	2021-03-15 06:04:38 +00:00
cannonlake	soc/intel/*: drop UART pad configuration from common code	2021-03-12 08:48:03 +00:00
common	pciexp_device: Rewrite LTR configuration	2021-03-15 06:04:38 +00:00
denverton_ns	soc/intel/denverton_ns: Drop pcidev_path_on_root_debug usage	2021-02-27 09:40:17 +00:00
elkhartlake	soc/intel/*: drop UART pad configuration from common code	2021-03-12 08:48:03 +00:00
icelake	soc/intel/*: drop UART pad configuration from common code	2021-03-12 08:48:03 +00:00
jasperlake	soc/intel/*: drop UART pad configuration from common code	2021-03-12 08:48:03 +00:00
quark	mainboards: Drop PWRS from GNVS	2021-02-11 16:35:32 +00:00
skylake	soc/intel/*: drop UART pad configuration from common code	2021-03-12 08:48:03 +00:00
tigerlake	soc/intel/tigerlake: Remove obsolete CNVi Bluetooth PCI device	2021-03-15 06:27:15 +00:00
xeon_sp	soc/intel/xeon_sp: Set SMI lock	2021-03-09 16:51:13 +00:00
Kconfig