Go to file
Furquan Shaikh bce8bb6e6c google/chromeec: Add elog events for recovery mode switches
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Verified eventlog on reef

0 | 2016-11-12 19:49:25 | Log area cleared | 4088
1 | 2016-11-12 19:49:25 | Kernel Event | Clean Shutdown
2 | 2016-11-12 19:49:25 | ACPI Enter | S5
3 | 2016-11-12 19:49:39 | System boot | 365
4 | 2016-11-12 19:49:39 | EC Event | Power Button
5 | 2016-11-12 19:49:45 | Chrome OS Recovery Mode | Recovery Button
Pressed
6 | 2016-11-12 19:49:45 | Chrome OS Developer Mode
7 | 2016-11-12 19:49:45 | EC Event | Keyboard Recovery
8 | 2016-11-12 19:49:45 | Memory Cache Update | Recovery | Success
9 | 2016-11-12 19:50:46 | System boot | 366
10 | 2016-11-12 19:50:46 | EC Event | Power Button
11 | 2016-11-12 19:50:52 | Chrome OS Recovery Mode | Recovery Button
Pressed
12 | 2016-11-12 19:50:52 | Chrome OS Developer Mode
13 | 2016-11-12 19:50:52 | EC Event | Keyboard Recovery Forced Hardware
Reinit
14 | 2016-11-12 19:50:52 | Memory Cache Update | Recovery | Success
15 | 2016-11-12 19:51:24 | Power Button
16 | 2016-11-12 19:51:24 | ACPI Enter | S5
17 | 2016-11-12 19:51:27 | System boot | 367
18 | 2016-11-12 19:51:27 | EC Event | Power Button
19 | 2016-11-12 19:51:32 | Wake Source | Power Button | 0
20 | 2016-11-12 19:51:32 | ACPI Wake | S5
21 | 2016-11-12 19:51:32 | Chrome OS Developer Mode
22 | 2016-11-12 19:51:32 | Memory Cache Update | Normal | Success

Change-Id: I45dda210cf9d4e5a75404792fcee15b2010787a7
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17394
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14 20:15:03 +01:00
3rdparty 3rdparty/vboot: update to latest master 2016-11-10 00:57:27 +01:00
Documentation Documentation: Add Kconfig document 2016-11-13 21:41:44 +01:00
payloads Do not select SEABIOS_VGA_COREBOOT by default when building for QEMU 2016-10-27 18:52:30 +02:00
src google/chromeec: Add elog events for recovery mode switches 2016-11-14 20:15:03 +01:00
util util/amdfwtool: unify return values, verify the file open 2016-11-10 00:26:45 +01:00
.checkpatch.conf Update .checkpatch.conf 2016-09-02 18:22:04 +02:00
.clang-format
.gitignore .gitignore: Add coreinfo build residue, defconfig 2016-09-02 18:20:51 +02:00
.gitmodules Set up 3rdparty/libgfxinit 2016-10-29 01:35:03 +02:00
.gitreview
COPYING
MAINTAINERS MAINTAINERS: Add lowrisc files to RISC-V 2016-11-12 19:30:26 +01:00
Makefile Makefile: Allow inclusion of source files from 3rdparty/ 2016-10-29 01:34:06 +02:00
Makefile.inc southbridge/amd: update for amdfwtool size on command line 2016-11-10 00:27:52 +01:00
README Remove extra newlines from the end of all coreboot files. 2016-07-31 18:19:33 +02:00
gnat.adc gnat.adc: Do not generate assertion code for Refined_Post 2016-10-29 01:33:31 +02:00
toolchain.inc Add minimal GNAT run time system (RTS) 2016-09-19 11:14:49 +02:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.