Balaji Manigandan B bd55c02a23 vendor/intel/skykabylake: Update FSP header files to version 2.7.2 ... Update FSP header files to version 2.7.2. New UPDs added FspmUpd.h: *CleanMemory FspsUpd.h: *IslVrCmd *ThreeStrikeCounterDisable Structure member names used to specify memory configuration to MRC have been updated, SoC side romstage code is updated to handle this change. CQ-DEPEND=CL:*460573,CL:*460612,CL:*460592 BUG=b:65499724 BRANCH=None TEST= Build and boot soraka, basic sanity check and suspend resume checks. Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151 Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>		2017-10-05 17:45:46 +00:00
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amd	AGESA vendorcode: Add ENABLE_MRC_CACHE option	2017-10-05 13:23:27 +00:00
google	Rename __attribute__((packed)) --> __packed	2017-07-13 19:45:59 +00:00
intel	vendor/intel/skykabylake: Update FSP header files to version 2.7.2	2017-10-05 17:45:46 +00:00
siemens	vendorcode/siemens: Add LegacyDelay to hwilib	2017-09-13 16:22:26 +00:00
Makefile.inc	vendorcode/siemens: Add hwilib for Siemens specific info struct	2016-04-28 08:15:47 +02:00