coreboot-kgpe-d16/src
Lin Huang bdd06de15d rockchip/rk3399: initialize apll_b
coreboot boots from the little core, and doesn't use the big core for
now, but if apll_b is set to the default 24MHz, it will take a long time
to enable the big core.  This will cause a watchdog crash, so apll_b
initialization to 600MHz needs to be done in coreboot.

BRANCH=none
BUG=chrome-os-partner:54817
TEST=Pick CL:353762 and see big CPU clocks look right
TEST=Boot from Gru and see no cpufreq warnings

Change-Id: Ie45cd2271555942e4321e9a9e523dc10f63d8107
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id:
Original-Change-Id: I20b8b591db3171e27740d85edce11f9e8797d849
Original-Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Original-Commit-Id: 16bc916174042620bebe19ae73d241002491aecc
Original-Original-Change-Id: Id3487138b383b6643ba7e3ce1eae501a6622da10
Original-Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Original-Reviewed-on: https://chromium-review.googlesource.com/356399
Original-Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15583
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-12 00:27:52 +02:00
..
acpi
arch acpi: Change device properties to work as a tree 2016-07-08 17:21:26 +02:00
commonlib region: Add writeat and eraseat support 2016-06-24 20:48:12 +02:00
console
cpu intel post-car: Consolidate choose_top_of_stack() 2016-07-10 11:16:07 +02:00
device device: i2c: Add support for I2C bus operations 2016-06-09 17:05:40 +02:00
drivers tpm: report firmware version 2016-07-12 00:26:42 +02:00
ec google/chromeec: Update EC command header 2016-07-10 03:54:07 +02:00
include vboot2: tpm2 factory initialization. 2016-07-12 00:27:27 +02:00
lib tpm2: add marshaling/unmarshaling layer 2016-07-11 23:52:56 +02:00
mainboard Gale: Add LED support. 2016-07-12 00:25:25 +02:00
northbridge nb/intel/x4x: Fix underclocking of 800MHz DDR2 RAM 2016-07-09 13:49:00 +02:00
soc rockchip/rk3399: initialize apll_b 2016-07-12 00:27:52 +02:00
southbridge PCI: Use PCI_DEVFN macro instead of DEV_FUNC 2016-07-06 21:58:09 +02:00
superio
vendorcode vboot2: tpm2 factory initialization. 2016-07-12 00:27:27 +02:00
Kconfig Romstage spinlocks require EARLY_CBMEM_INIT 2016-07-10 04:03:31 +02:00