Aaron Durbin be2512973d ramstage_cache: allow ramstage usage add valid helper ... Allow ramstage cache to be used from ramstage proper. Also add a helper function for checking validity of ramstage cache structure. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: If1f2ad1bcf64504b42e315be243a12432b50e3d5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179775 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5011 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>		2014-05-10 06:31:45 +02:00
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arch	Introduce stage-specific architecture for coreboot	2014-05-06 20:23:31 +02:00
console	console: Fix UART selection prompt	2014-04-30 23:47:28 +02:00
cpu	cougar_canyon2: Switch CPU/NB/SB to the shared FSP code	2014-05-09 21:36:12 +02:00
device	Introduce stage-specific architecture for coreboot	2014-05-06 20:23:31 +02:00
drivers	Intel FSP: add a shared set of functions for the FSP	2014-05-09 21:35:56 +02:00
ec	baytrail: Basic DPTF framework	2014-05-09 05:42:52 +02:00
include	ramstage_cache: allow ramstage usage add valid helper	2014-05-10 06:31:45 +02:00
lib	ramstage_cache: allow ramstage usage add valid helper	2014-05-10 06:31:45 +02:00
mainboard	cougar_canyon2: Switch CPU/NB/SB to the shared FSP code	2014-05-09 21:36:12 +02:00
northbridge	cougar_canyon2: Switch CPU/NB/SB to the shared FSP code	2014-05-09 21:36:12 +02:00
soc	baytrail: note S3 resume status earlier	2014-05-10 06:31:37 +02:00
southbridge	cougar_canyon2: Switch CPU/NB/SB to the shared FSP code	2014-05-09 21:36:12 +02:00
superio	superio/serverengines/pilot: Avoid .c includes	2014-05-09 08:26:14 +02:00
vendorcode	Declare get_write_protect_state() without ChromeOS	2014-05-08 16:25:30 +02:00
Kconfig	Intel FSP: add a shared set of functions for the FSP	2014-05-09 21:35:56 +02:00