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coreboot-kgpe-d16/src/northbridge
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Martin Roth 2dd3f877cc cougar_canyon2: Switch CPU/NB/SB to the shared FSP code 
CPU - fsp_model_206ax:
- Remove Kconfig options and mark this as using the FSP.
- Use shared FSP cache_as_ram.inc file
Mainboard - intel/cougar_canyon2:
- Update to use the shared FSP header file.
- Modify to call copy_and_run() directly instead of returning to
cache_as_ram.inc.
Northbridge - fsp_sandybridge:
- remove mrccache, fsp_util.[ch]
- add fsp/chipset_fsp_util.[ch] with chipset specific FSP bits.
- Update to use the shared FSP header file.

These changes were validated with FSP:
CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd
SHA256: e1bbd614058675636ee45f8dc1a6dbf0e818bcdb32318b7f8d8b6ac0ce730801
MD5: 24965382fbb832f7b184d3f24157abda

Change-Id: Ibc52a78312c2fcbd1e632bc2484e4379a4f057d4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5636
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-09 21:36:12 +02:00
..
amd AGESA: Implement EmptyHeap() 2014-05-05 08:53:50 +02:00
dmp CBMEM northbridges: Remove references to global high_tables_base 2013-09-11 07:09:47 +02:00
intel cougar_canyon2: Switch CPU/NB/SB to the shared FSP code 2014-05-09 21:36:12 +02:00
rdc CBMEM northbridges: Remove references to global high_tables_base 2013-09-11 07:09:47 +02:00
via via: Write »access« without »m« at end 2013-12-27 19:49:46 +01:00
Kconfig Add support for DMP Vortex86EX PCI northbridge. 2013-06-22 17:33:27 +02:00
Makefile.inc Add support for DMP Vortex86EX PCI northbridge. 2013-06-22 17:33:27 +02:00