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Aaron Durbin c12ef9723e haswell: resource allocation
The previous code w.r.t. resource allocation was getting lucky
based on the way fixed mmio resources on the system were being
chosen. Namely, PCIEXBAR was the lowest mmio space and the other
fixed non-standar BARs were above it. The resource allocator would
then start allocating standard BARs below that.

On top of that other resources were being added when
dev_ops->set_resources() was being called on the PCI domain. At that
point the PCI range limit were already picked for where to start
allocating from.

To ensure we no longer get lucky during resource allocation add the
fixed resources in the host bridge and add the memory controller
cacheable memory areas. With those resources added the range limit
for standard PCI BARs is chosen properly.

Depending on haswell board configurations we may need to adjust and
pass in the size of physical address space needed for PCI resources
to the reference code. For the time being the CRBs appear to be OK.

Lastly, remove the SNB workaround for reserving 2MiB at 1GiB and 512MiB.

Output from 6GiB memory configuration:
	MC MAP: TOM: 0x140000000
	MC MAP: TOUUD: 0x18f600000
	MC MAP: MESEG_BASE: 0x13f000000
	MC MAP: MESEG_LIMIT: 0x7fff0fffff
	MC MAP: REMAP_BASE: 0x13f000000
	MC MAP: REMAP_LIMIT: 0x18f5fffff
	MC MAP: TOLUD: 0xafa00000
	MC MAP: BDSM: 0xada00000
	MC MAP: BGSM: 0xad800000
	MC MAP: TESGMB: 0xad000000
	MC MAP: GGC: 0x209

	coreboot memory table:
	 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
	 1. 0000000000001000-000000000009ffff: RAM
	 2. 00000000000a0000-00000000000fffff: RESERVED
	 3. 0000000000100000-0000000000efffff: RAM
	 4. 0000000000f00000-0000000000ffffff: RESERVED
	 5. 0000000001000000-00000000acebffff: RAM
	 6. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES
	 7. 00000000ad000000-00000000af9fffff: RESERVED
	 8. 00000000f0000000-00000000f3ffffff: RESERVED
	 9. 00000000fed10000-00000000fed17fff: RESERVED
	10. 00000000fed18000-00000000fed18fff: RESERVED
	11. 00000000fed19000-00000000fed19fff: RESERVED
	12. 00000000fed84000-00000000fed84fff: RESERVED
	13. 0000000100000000-000000018f5fffff: RAM

	e820 map has 11 items:
	  0: 0000000000000000 - 000000000009fc00 = 1 RAM
	  1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
	  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
	  3: 0000000000100000 - 0000000000f00000 = 1 RAM
	  4: 0000000000f00000 - 0000000001000000 = 2 RESERVED
	  5: 0000000001000000 - 00000000acec0000 = 1 RAM
	  6: 00000000acec0000 - 00000000afa00000 = 2 RESERVED
	  7: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
	  8: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
	  9: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
	  10: 0000000100000000 - 000000018f600000 = 1 RAM

Output from 4GiB memory configuration:
	MC MAP: TOM: 0x100000000
	MC MAP: TOUUD: 0x14f600000
	MC MAP: MESEG_BASE: 0xff000000
	MC MAP: MESEG_LIMIT: 0x7fff0fffff
	MC MAP: REMAP_BASE: 0x100000000
	MC MAP: REMAP_LIMIT: 0x14f5fffff
	MC MAP: TOLUD: 0xafa00000
	MC MAP: BDSM: 0xada00000
	MC MAP: BGSM: 0xad800000
	MC MAP: TESGMB: 0xad000000
	MC MAP: GGC: 0x209

	coreboot memory table:
	 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
	 1. 0000000000001000-000000000009ffff: RAM
	 2. 00000000000a0000-00000000000fffff: RESERVED
	 3. 0000000000100000-0000000000efffff: RAM
	 4. 0000000000f00000-0000000000ffffff: RESERVED
	 5. 0000000001000000-00000000acebffff: RAM
	 6. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES
	 7. 00000000ad000000-00000000af9fffff: RESERVED
	 8. 00000000f0000000-00000000f3ffffff: RESERVED
	 9. 00000000fed10000-00000000fed17fff: RESERVED
	10. 00000000fed18000-00000000fed18fff: RESERVED
	11. 00000000fed19000-00000000fed19fff: RESERVED
	12. 00000000fed84000-00000000fed84fff: RESERVED
	13. 0000000100000000-000000014f5fffff: RAM

	e820 map has 11 items:
	  0: 0000000000000000 - 000000000009fc00 = 1 RAM
	  1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
	  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
	  3: 0000000000100000 - 0000000000f00000 = 1 RAM
	  4: 0000000000f00000 - 0000000001000000 = 2 RESERVED
	  5: 0000000001000000 - 00000000acec0000 = 1 RAM
	  6: 00000000acec0000 - 00000000afa00000 = 2 RESERVED
	  7: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
	  8: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
	  9: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
	  10: 0000000100000000 - 000000014f600000 = 1 RAM

Output from 2GiB memory configuration:
	MC MAP: TOM: 0x40000000
	MC MAP: TOUUD: 0x100600000
	MC MAP: MESEG_BASE: 0x3f000000
	MC MAP: MESEG_LIMIT: 0x7fff0fffff
	MC MAP: REMAP_BASE: 0x100000000
	MC MAP: REMAP_LIMIT: 0x1005fffff
	MC MAP: TOLUD: 0x3ea00000
	MC MAP: BDSM: 0x3ca00000
	MC MAP: BGSM: 0x3c800000
	MC MAP: TESGMB: 0x3c000000
	MC MAP: GGC: 0x209

	coreboot memory table:
	 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
	 1. 0000000000001000-000000000009ffff: RAM
	 2. 00000000000a0000-00000000000fffff: RESERVED
	 3. 0000000000100000-0000000000efffff: RAM
	 4. 0000000000f00000-0000000000ffffff: RESERVED
	 5. 0000000001000000-000000003bebffff: RAM
	 6. 000000003bec0000-000000003bffffff: CONFIGURATION TABLES
	 7. 000000003c000000-000000003e9fffff: RESERVED
	 8. 00000000f0000000-00000000f3ffffff: RESERVED
	 9. 00000000fed10000-00000000fed17fff: RESERVED
	10. 00000000fed18000-00000000fed18fff: RESERVED
	11. 00000000fed19000-00000000fed19fff: RESERVED
	12. 00000000fed84000-00000000fed84fff: RESERVED
	13. 0000000100000000-00000001005fffff: RAM

	e820 map has 11 items:
	  0: 0000000000000000 - 000000000009fc00 = 1 RAM
	  1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
	  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
	  3: 0000000000100000 - 0000000000f00000 = 1 RAM
	  4: 0000000000f00000 - 0000000001000000 = 2 RESERVED
	  5: 0000000001000000 - 000000003bec0000 = 1 RAM
	  6: 000000003bec0000 - 000000003ea00000 = 2 RESERVED
	  7: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
	  8: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
	  9: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
	  10: 0000000100000000 - 0000000100600000 = 1 RAM

Verified through debug messages that range limits as well as
resources were being properly honored.

Change-Id: I2faa7d8a2a34a6a411a2885afb3b5c3fa1ad9c23
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2687
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-03-15 15:24:31 +01:00
3rdparty@dac1a18d18 Eagleheights DSDT: Grant OS control through OSC 2013-03-13 23:44:00 +01:00
documentation sconfig: rename lapic_cluster -> cpu_cluster 2013-02-14 07:07:20 +01:00
payloads libpayload: add support for vboot_handoff 2013-03-14 04:57:03 +01:00
src haswell: resource allocation 2013-03-15 15:24:31 +01:00
util GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
.gitignore add a few entries to .gitignore 2013-01-10 22:51:20 +01:00
.gitmodules Add 3rdparty as submodule 2012-05-01 00:08:37 +02:00
.gitreview add .gitreview 2012-11-01 23:13:39 +01:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
Makefile build system: Retire REQUIRES_BLOB 2013-02-19 11:00:41 +01:00
Makefile.inc x86: SMM Module Support 2013-03-14 05:01:50 +01:00
README Update README with newer version of the text from the web page 2011-06-15 10:16:33 +02:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * gcc / g++
 * make

Optional:

 * doxygen (for generating/viewing documentation)
 * iasl (for targets with ACPI support)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.