coreboot-kgpe-d16/src/vendorcode
Kane Chen c024381f8f vendorcode/intel/fsp/fsp2_0/glk: Add nWR config in Odt Config
From doc 571118, the bit 5 of OdtConfig is nWR config.
If the bit 5 is set, MRC will set MR1 nWR field to 24.
If the bit 5 is clear, MRC will set MR1 nWR field to 6.

Change-Id: Ic8e4e2ffb098c8ba2f670535981e9a30c3d45b64
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/27814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-06 07:56:47 +00:00
..
amd src/vendorcode/amd/pi/00670F00: Remove IMC support 2018-07-31 00:46:25 +00:00
cavium vendorcode/cavium/include: Make bdk_pop and dpop static 2018-07-17 11:38:28 +00:00
google intel/wifi: Add WGDS ACPI method for Geo Aware SAR 2018-07-13 10:42:04 +00:00
intel vendorcode/intel/fsp/fsp2_0/glk: Add nWR config in Odt Config 2018-08-06 07:56:47 +00:00
siemens src: Fix all Siemens copyrights 2017-11-07 12:33:51 +00:00
Makefile.inc soc/cavium: Integrate BDK files into coreboot 2018-07-03 15:53:32 +00:00