Furquan Shaikh 6d5e10c05d soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array ... This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ# from mainboards instead of defining a separate property for each root port. This allows us to use memcpy to copy the entire array into FSP params as well as new properties for PCIe root ports can be added as arrays in future CLs. BUG=b:74633273 BRANCH=reef,coral Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2018-03-16 04:43:01 +00:00
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acpi_tables.c
board_info.txt
bootblock.c	soc/intel/common/block: Add LPC Common code and use it for APL	2017-08-15 19:59:21 +00:00
brd_gpio.h	mainboard/intel/leafhill: Clean up	2017-02-25 09:00:50 +01:00
devicetree.cb	soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array	2018-03-16 04:43:01 +00:00
dsdt.asl
Kconfig	mainboard/intel/leafhill: Clean up	2017-02-25 09:00:50 +01:00
Kconfig.name	Fix files with multiple newlines at the end.	2017-07-24 15:08:08 +00:00
leafhill.8192.fmd	mainboard/intel/leafhill: Clean up	2017-02-25 09:00:50 +01:00
leafhill.16384.fmd	mainboard/intel/leafhill: Clean up	2017-02-25 09:00:50 +01:00
mainboard.c
Makefile.inc	mainboard/intel/leafhill: Clean up	2017-02-25 09:00:50 +01:00
romstage.c