Wonkyu Kim c332a47c54 soc/intel/tigerlake: Disable image clocks ... TGL FSP does just pin mux for image clock pins by UPD and image clocks are controlled by ACPI(camera_clock_ctl.asl) under tigerlake SOC folder. Disable image clocks by UPD for bypassing FSP pin mux and do pin mux in gpio.c according to board design. BUG=none BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I5aba5b2fb6deee231e3ec34c8dbc9972b01041f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38562 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-01-29 10:28:02 +00:00
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apollolake	intel/apollolake: Remove CBFS locator override	2020-01-18 10:50:50 +00:00
baytrail	sb/intel/common: Declare common smbus_base() and enable_smbus()	2020-01-14 18:18:26 +00:00
braswell	device,sb/intel: Move SMBus host controller prototypes	2020-01-09 21:25:41 +00:00
broadwell	sb/intel/common: Declare common smbus_base() and enable_smbus()	2020-01-14 18:18:26 +00:00
cannonlake	soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs	2020-01-18 12:03:17 +00:00
common	drivers/spi/spi_flash: remove spi flash names	2020-01-28 14:44:37 +00:00
denverton_ns	sb/intel/common: Add smbus_set_slave_addr()	2020-01-09 21:31:31 +00:00
icelake	soc/intel/{cnl,icl,skl, tgl}: Move SOC_INTEL_COMMON_BLOCK_THERMAL into SoC specific Kconfig	2020-01-16 16:28:09 +00:00
quark	{nb,soc}: Replace min/max() with MIN/MAX()	2019-12-20 17:46:37 +00:00
skylake	soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet	2020-01-26 03:01:04 +00:00
tigerlake	soc/intel/tigerlake: Disable image clocks	2020-01-29 10:28:02 +00:00
Kconfig	soc/intel/Kconfig: Load Tiger Lake SOC Kconfig	2019-12-11 11:37:45 +00:00