9231f0b92a
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic875708697f07b6dae09d27dbd67eb8b960749f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
161 lines
5.4 KiB
Makefile
161 lines
5.4 KiB
Makefile
## SPDX-License-Identifier: GPL-2.0-only
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ifeq ($(CONFIG_SOC_NVIDIA_TEGRA210),y)
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CBOOTIMAGE_OPTS = --soc tegra210
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bootblock-y += bootblock.c
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bootblock-y += bootblock_asm.S
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bootblock-y += clock.c
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bootblock-y += spi.c
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bootblock-y += i2c.c
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bootblock-y += dma.c
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bootblock-y += monotonic_timer.c
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bootblock-y += padconfig.c
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bootblock-y += power.c
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bootblock-y += funitcfg.c
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bootblock-y += ../tegra/gpio.c
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bootblock-y += ../tegra/i2c.c
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bootblock-y += ../tegra/pingroup.c
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bootblock-y += ../tegra/pinmux.c
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bootblock-y += ../tegra/apbmisc.c
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bootblock-y += ../tegra/usb.c
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bootblock-y += uart.c
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verstage-y += dma.c
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verstage-y += monotonic_timer.c
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verstage-y += spi.c
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verstage-y += padconfig.c
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verstage-y += funitcfg.c
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verstage-y += uart.c
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verstage-y += ../tegra/gpio.c
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verstage-y += ../tegra/i2c.c
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verstage-y += ../tegra/pinmux.c
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verstage-y += clock.c
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verstage-y += i2c.c
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romstage-y += romstage_asm.S
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romstage-y += addressmap.c
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romstage-y += cbmem.c
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romstage-y += ccplex.c
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romstage-y += clock.c
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romstage-y += cpu.c
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romstage-y += spi.c
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romstage-y += i2c.c
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romstage-y += dma.c
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romstage-y += monotonic_timer.c
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romstage-y += padconfig.c
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romstage-y += funitcfg.c
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romstage-y += romstage.c
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romstage-y += power.c
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romstage-y += ram_code.c
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ifneq ($(CONFIG_BOOTROM_SDRAM_INIT),y)
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romstage-y += sdram.c
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romstage-y += sdram_lp0.c
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endif
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romstage-y += ../tegra/gpio.c
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romstage-y += ../tegra/i2c.c
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romstage-y += ../tegra/pinmux.c
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romstage-y += ../tegra/usb.c
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romstage-y += uart.c
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ramstage-y += addressmap.c
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ramstage-y += cbmem.c
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ramstage-y += cpu.c
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ramstage-y += clock.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += dc.c
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ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += dsi.c
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ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += mipi_dsi.c
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ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += mipi.c
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ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += mipi-phy.c
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ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += ./jdi_25x18_display/panel-jdi-lpm102a188a.c
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ramstage-$(CONFIG_MAINBOARD_DO_SOR_INIT) += dp.c
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ramstage-$(CONFIG_MAINBOARD_DO_SOR_INIT) += sor.c
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ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += arm_tf.c
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ramstage-y += sdram_lp0.c
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ramstage-y += soc.c
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ramstage-y += spi.c
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ramstage-y += i2c.c
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ramstage-y += i2c6.c
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ramstage-y += ape.c
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ramstage-y += power.c
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ramstage-y += dma.c
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ramstage-y += monotonic_timer.c
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ramstage-y += padconfig.c
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ramstage-y += funitcfg.c
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ramstage-y += ram_code.c
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ramstage-y += ../tegra/apbmisc.c
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ramstage-y += ../tegra/gpio.c
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ramstage-y += ../tegra/i2c.c
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ramstage-y += ../tegra/pinmux.c
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ramstage-y += ramstage.c
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ramstage-y += mmu_operations.c
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ramstage-y += uart.c
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ramstage-y += ../tegra/usb.c
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ramstage-$(CONFIG_HAVE_MTC) += mtc.c
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ramstage-y += stage_entry.S
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rmodules_arm-y += monotonic_timer.c
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CPPFLAGS_common += -Isrc/soc/nvidia/tegra210/include/
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# We want to grab the bootblock right before it goes into the image and wrap
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# it inside a BCT, but ideally we would do that without making special, one
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# use modifications to the main ARM Makefile. We do this in two ways. First,
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# we copy bootblock.elf to bootblock.raw.elf and allow the %.bin: %.elf
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# template rule to turn it into bootblock.raw.bin. This makes sure whatever
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# processing is supposed to happen to turn an .elf into a .bin happens.
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#
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# Second, we add our own rule for creating bootblock.bin from
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# bootblock.raw.bin which displaces the template rule. When other rules that
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# package up the image pull in bootblock.bin, it will be this wrapped version
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# instead of the raw bootblock.
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$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
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cp $< $@
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$(obj)/generated/bct.bin: $(obj)/generated/bct.cfg $(CBOOTIMAGE)
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@printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n"
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$(CBOOTIMAGE) -gbct $(CBOOTIMAGE_OPTS) $< $@
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BCT_BIN = $(obj)/generated/bct.bin
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BCT_WRAPPER = $(obj)/generated/bct.wrapper
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$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BCT_BIN)
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echo "Version = 1;" > $(BCT_WRAPPER)
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echo "Redundancy = 1;" >> $(BCT_WRAPPER)
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echo "Bctcopy = 1;" >> $(BCT_WRAPPER)
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echo "Bctfile = $(BCT_BIN);" >> $(BCT_WRAPPER)
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echo "BootLoader = $<,$(call loadaddr,bootblock),$(call loadaddr,bootblock),Complete;" >> $(BCT_WRAPPER)
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@printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n"
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$(CBOOTIMAGE) $(CBOOTIMAGE_OPTS) $(BCT_WRAPPER) $@
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# We need to ensure that TZ memory has enough space to hold TTB and resident EL3
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# components (including BL31 and Secure OS)
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ttb_size=$(shell printf "%d" $(CONFIG_TTB_SIZE_MB))
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sec_size=$(shell printf "%d" $(CONFIG_SEC_COMPONENT_SIZE_MB))
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req_tz_size=$(shell expr $(ttb_size) + $(sec_size))
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tz_size=$(shell printf "%d" $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB))
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ifeq ($(shell test $(tz_size) -lt $(req_tz_size) && echo 1), 1)
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$(error "TRUSTZONE_CARVEOUT_SIZE_MB should be at least as big as TTB_SIZE_MB + SEC_COMPONENT_SIZE_MB")
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endif
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# BL31 component is placed towards the end of 32-bit address space. This assumes
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# that TrustZone memory is placed at the end of 32-bit address space. Within the
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# TZ memory, we place BL31 and BL32(if available) towards the beginning and TTB
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# towards the end. Calculate TZDRAM_BASE i.e. base of BL31 component by:
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# 0x1000 = end of 32-bit address space in MiB
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# 0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) = start of TZ memory in MiB
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BL31_MAKEARGS += TZDRAM_BASE=$$(((0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB)) << 20))
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BL31_MAKEARGS += PLAT=tegra TARGET_SOC=t210
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# MTC fw
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MTC_DIR = $(CONFIG_MTC_DIRECTORY)
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MTC_FILE = $(MTC_DIR)/$(CONFIG_MTC_FILE)
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MTC_FILE_CBFS = $(CONFIG_MTC_FILE)
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cbfs-files-$(CONFIG_HAVE_MTC) += $(MTC_FILE_CBFS)
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$(MTC_FILE_CBFS)-file := $(MTC_FILE)
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$(MTC_FILE_CBFS)-type := raw
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endif
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