fef509499f
The ASUS KFSN4-DRE has a physical BIOS recovery jumper; force coreboot into fallback mode if that jumper is set. Change-Id: I513299c3e3261fc76133a49813685d48c53a172a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9156 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
69 lines
2.5 KiB
Text
69 lines
2.5 KiB
Text
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SPD mux
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DIMM_A1 SDA signal traced to U6 pin 1
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Destructive testing of failed board (removal of U7 northbridge!) yielded the following information:
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U6 S0 <--> U7 W2
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U6 S1 <--> U7 W3
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Proprietary BIOS enables the SPD during POST with:
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S0: LOW
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S1: LOW
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then temporarily switches to:
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S0: LOW
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S1: HIGH
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then switches to runtime mode with:
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S0: HIGH
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S1: LOW
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After probing with a custom GPIO-flipping tool under Linux the following GPIO mappings were found:
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CK804 pin W2 <--> GPIO43
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CK804 pin W3 <--> GPIO44
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W83793 (U46)
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Sensor mappings:
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FRNT_FAN1: FAN3
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FRNT_FAN2: FAN4
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FRNT_FAN3: FAN5
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FRNT_FAN4: FAN6
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FRNT_FAN5: FAN9
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FRNT_FAN6: FAN10
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REAR_FAN1: FAN7
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REAR_FAN2: FAN8
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REAR_FAN3: FAN11
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REAR_FAN4: FAN12
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====================================================================================================
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Other hardware
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Power LED (-) is connected to U15 (SuperIO) pin 64 via U4 pins 5,6 and a small MOSFET
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ID LED (-) is connected to a ??? via U4 pins 1,2,3,4 and U77 pins 5,6
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It appears that setting U15 (SuperIO) pin 88 LOW will override the ID LED and force it ON
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RECOVERY2 middle pin is connected to U15 (SuperIO) pin 89
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Normal is HIGH, recovery is LOW.
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PCIe slot WAKE# connects to U7 pin E23 (PCIE_WAKE#)
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CPU_WARN1 is driven by (???) via a simple buffer (U13 pin 10)
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MEM_WARN1 is driven by U7 pin AD3 (CPUVDD_EN) via a simple buffer (U101 pin 3)
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U7 pin AK3 is disconnected (routed to unpopulated capacitor/resistor)
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PU1 pin 37 (VDDPWRGD) drives U7 pin AJ4 (CPU_VLD)
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A small MOSFET directly above another small MOSFET directly above the right-hand edge of the PCIe slot drives U7 pin AK5 (HT_VLD)
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When > Barcelona CPU installed on PCB rev 1.04G:
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U7 pin AK4 (MEM_VLD): HIGH
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PU1 pin 37: LOW
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U7 pin AK5: LOW
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HyperTransport 1.2V supply appears to be generated by a linear regulator containing Q191 and downconverting the CK804 1.5V supply
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The enable pin appears to be tied to AUX_PANEL pin 1 (+5VSB) via a resistor
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Through two MOSFETs the HT supply enable pin is tied to U7 pin AE3 (HTVDD_EN)
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