Furquan Shaikh c681409a8a soc/intel/apollolake: Correct PCI write size in romstage ... 1. PCI command reg write should be 16-bit. 2. HPTC reg write should be 8-bit. Also, use macros instead of hard-coded values. Currently, the macros are defined in romstage.c, but if more P2SB macros are added, it would be good to move them to a separate header file. Change-Id: Iad1eb6a95467a41ecf454092808d357425c4c2fc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14613 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>		2016-05-06 06:52:28 +02:00
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broadcom/cygnus	soc/*: fix uart's regwidth specification in cbtables	2016-02-21 12:26:05 +01:00
dmp/vortex86ex	dmp/vortex86ex: Merge northbridge and southbridge into soc	2016-05-05 20:06:33 +02:00
imgtec/pistachio	imgtec/pistachio: Fix memlayout ASSERT with new binutils	2016-04-21 07:16:06 +02:00
intel	soc/intel/apollolake: Correct PCI write size in romstage	2016-05-06 06:52:28 +02:00
marvell	src/soc/marvell: Update license headers	2016-04-13 17:34:33 +02:00
mediatek/mt8173	mediatek/mt8173: fix incorrect indent	2016-04-05 13:35:50 +02:00
nvidia	edid: Make framebuffer row alignment configurable	2016-04-07 20:46:38 +02:00
qualcomm/ipq806x	ipq806x/storm: Return NULL for cbmem_top if DRAM is not initialized	2016-03-29 22:37:01 +02:00
rdc/r8610	rdc/r8610: Move to src/soc	2016-05-05 20:08:58 +02:00
rockchip	google/gru: Incorporate feedback to #14279	2016-04-16 02:01:51 +02:00
samsung	soc/*: fix uart's regwidth specification in cbtables	2016-02-21 12:26:05 +01:00
ucb/riscv	tree: drop last paragraph of GPL copyright header	2015-10-31 21:37:39 +01:00