coreboot-kgpe-d16/Documentation/soc
Marshall Dawson 5b43484db3 Documentation/soc/amd/family17: Update to match current design
The Picasso no longer intends to implement a hybrid romstage,
opting instead for a more traditional bootblock/romstage/ramstage.
Update the documentation to reflect this.  Clarify additional
details that have come to light since the last revision.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I6c98c007ddb8a4a05810f19e4215bde719de7bb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-11 07:52:04 +00:00
..
amd Documentation/soc/amd/family17: Update to match current design 2020-02-11 07:52:04 +00:00
cavium Documentation: Fix markdown highlighting 2018-10-22 12:02:15 +00:00
intel docs: intel fsp: add memory retraining bug on SPS systems 2019-11-19 12:56:10 +00:00
qualcomm sc7180: Provide initial SoC support 2019-10-21 09:06:55 +00:00
index.md sc7180: Provide initial SoC support 2019-10-21 09:06:55 +00:00