Felix Held c86acf4216 soc/amd/cezanne: populate some FSP-M UPDs ... Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I81a812662f921d0bf8d436238d338b6a1fa6a9ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/50239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>		2021-02-05 15:44:02 +00:00
..
include/soc	soc/amd/cezanne: remove UART2/3 AOAC device offsets	2021-02-03 19:59:54 +00:00
aoac.c	soc/amd/cezanne: add AOAC support	2021-01-14 15:42:34 +00:00
bootblock.c	soc/amd/cezanne: add caching setup in bootblock	2020-12-13 22:18:03 +00:00
chip.c	soc/amd/cezanne: add use result of acpi_is_wakeup_s3() in FSP calls	2021-01-30 17:17:24 +00:00
chip.h	soc/amd/cezanne: add config.c and minimal chip.h	2020-12-06 19:05:47 +00:00
chipset.cb	soc/amd/cezzane: Add a minimal chipset tree	2021-01-11 07:42:12 +00:00
config.c	soc/amd/cezanne: add config.c and minimal chip.h	2020-12-06 19:05:47 +00:00
early_fch.c	soc/amd/cezanne: add AOAC support	2021-01-14 15:42:34 +00:00
fch.c	soc/amd/cezanne: add empty ramstage FCH support	2021-01-29 22:57:01 +00:00
fsp_params.c	soc,vendorcode/amd/cezanne: add basic FSP integration	2021-01-24 18:15:46 +00:00
fw.cfg	amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73)	2021-02-03 13:48:51 +00:00
gpio.c	soc/amd/cezanne: add GPIO support	2020-12-18 17:20:56 +00:00
Kconfig	soc/amd/cezanne/Kconfig: select common PSP gen2 support	2021-01-31 01:13:04 +00:00
Makefile.inc	soc/amd/cezanne: add empty ramstage FCH support	2021-01-29 22:57:01 +00:00
reset.c	soc/amd/cezanne: add 0xcf9 reset	2020-12-11 17:44:42 +00:00
romstage.c	soc/amd/cezanne: populate some FSP-M UPDs	2021-02-05 15:44:02 +00:00
uart.c	soc/amd/cezanne,picasso/uart: remove unneeded struct name	2021-01-15 01:19:59 +00:00