John Zhao f3a8bf13cb soc/intel/alderlake: Drop 100ms delay and do not poll Link Active ... Drop the 100ms delay in the _PS0 method because kernel already adds this 100ms. This change also drops polling TBT PCIe root ports Link Active State because this scheme is not applicable for SW CM. BUG=None TEST=Built Alderlake coreboot image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I792d3c8ca4249ed74d4090ec1efba5a180429c75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51191 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-03-15 06:30:52 +00:00
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camera_clock_ctl.asl
dptf.asl
gpio.asl
pch_hda.asl
pci_irqs.asl	soc/intel/alderlake: Fix PCI IRQ tables	2021-02-17 22:28:13 +00:00
pcie.asl
serialio.asl
southbridge.asl	soc/intel: Include gfx.asl from northbridge	2021-03-01 08:32:47 +00:00
tcss.asl
tcss_dma.asl	soc/intel/alderlake: Remove _DSD from tcss_dma ASL file	2021-03-15 06:03:08 +00:00
tcss_pcierp.asl	soc/intel/alderlake: Drop 100ms delay and do not poll Link Active	2021-03-15 06:30:52 +00:00
tcss_xhci.asl
xhci.asl