Subrata Banik c8ac8f5ce9 soc/intel/alderlake: Align RcompResistor definition as per MRC ... List of changes: 1. Alder Lake MRC is expecting a RcompResistor value of word width. Reference RCOMP resistors on motherboard are ~ 100 Ohms but coreboot is passing an array of RcompResistor which is not completely in use. Note: Rcomp resistor value represents rcomp resistor attached to the DDR_COMP pins on the SoC. 2. Also, remove usage of '&' with memcpy the required value into RcompTarget array. 3. Also, update RcompResistor value for ADLRVP. BUG=b:183341229 TEST=Enable FSP debug log to verify the override value for RcompResistor is reflecting correctly. Change-Id: I69c7cec55b65036fc039c33374a3fd363ef7004e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>		2021-03-26 04:52:57 +00:00
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acpi	soc/intel/alderlake: Drop 100ms delay and do not poll Link Active	2021-03-15 06:30:52 +00:00
bootblock	soc/intel: Drop bootblock_cpu_init() function	2021-03-01 19:43:04 +00:00
include/soc	soc/intel/alderlake: Align RcompResistor definition as per MRC	2021-03-26 04:52:57 +00:00
romstage	soc/intel/alderlake: Enable CSE Lite driver for ADL platform in romstage	2021-03-17 08:01:14 +00:00
spd	util: Add new memory part to LP4x list	2021-03-03 15:50:47 +00:00
acpi.c	soc/intel: Factor out identical acpigen GPIO helpers	2021-03-01 19:37:56 +00:00
chip.c	soc/intel/{adl,jsl,ehl,tgl}: Remove ITSS polarity restore	2021-02-24 11:28:45 +00:00
chip.h	soc/intel/alderlake: Add CNVi Bluetooth flag at devicetree entry	2021-03-15 06:24:48 +00:00
chipset.cb	soc/intel/alderlake: Remove obsolete CNVi Bluetooth PCI device	2021-03-15 06:25:20 +00:00
cpu.c	src: Remove unused <arch/cpu.h>	2021-02-11 10:25:23 +00:00
elog.c	soc/intel/alderlake: Log internal device wake events	2021-03-03 09:04:12 +00:00
espi.c
finalize.c
fsp_params.c	soc/intel/alderlake: Add CNVi Bluetooth flag at devicetree entry	2021-03-15 06:24:48 +00:00
gpio.c
gspi.c
i2c.c
Kconfig	soc/intel/alderlake: Add Kconfig for recommended PCIe TBT resources	2021-03-15 06:03:31 +00:00
lockdown.c
Makefile.inc	soc/intel: Factor out common smmrelocate.c	2021-03-03 09:06:09 +00:00
me.c
meminit.c	soc/intel/alderlake: Align RcompResistor definition as per MRC	2021-03-26 04:52:57 +00:00
p2sb.c
pcie_rp.c
pmc.c
pmutil.c	soc/intel/*/pmutil.c: Align cosmetics across platforms	2021-02-24 11:34:42 +00:00
reset.c	soc/intel: Use of common reset code block	2020-11-02 10:43:53 +00:00
smihandler.c
soundwire.c
spi.c
systemagent.c
uart.c	soc/intel/*: drop UART pad configuration from common code	2021-03-12 08:48:03 +00:00
xhci.c	soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support	2021-02-24 11:27:51 +00:00