c99681f4f2
In order to avoid a 300ms timeout waiting for mbp_cleared flag to be set there is a new flow for the ME10 1.5MB firwmare that we can follow which will save significant boot time. This requires sending new commands that do not generate an ACK message, and ensuring an HMRFPO LOCK message is sent. In addition now that the delay is removed clean up the ME path to do the work in init() step and add a final() step that does the disabling of the PCI device. BUG=chrome-os-partner:30637,chrome-os-partner:34134 BRANCH=samus,auron TEST=build and boot on samus, measure ~300ms speedup in boot time Original-Change-Id: I753087ecd65f6ebed9f812318a359f893e01da9f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234400 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 25aff4b188dc94a99af30869a162e01e3fa8dee7) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia35373548a902a718155a1a57057f55067d2f3ac Reviewed-on: http://review.coreboot.org/9697 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
126 lines
4.1 KiB
C
126 lines
4.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <bootstate.h>
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#include <console/console.h>
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#include <console/post_codes.h>
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#include <cpu/x86/smm.h>
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#include <reg_script.h>
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#include <spi-generic.h>
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#include <stdlib.h>
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#include <soc/pci_devs.h>
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#include <soc/lpc.h>
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#include <soc/me.h>
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#include <soc/rcba.h>
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#include <soc/spi.h>
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#include <soc/systemagent.h>
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const struct reg_script system_agent_finalize_script[] = {
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REG_PCI_OR16(0x50, 1 << 0), /* GGC */
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REG_PCI_OR32(0x5c, 1 << 0), /* DPR */
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REG_PCI_OR32(0x78, 1 << 10), /* ME */
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REG_PCI_OR32(0x90, 1 << 0), /* REMAPBASE */
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REG_PCI_OR32(0x98, 1 << 0), /* REMAPLIMIT */
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REG_PCI_OR32(0xa0, 1 << 0), /* TOM */
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REG_PCI_OR32(0xa8, 1 << 0), /* TOUUD */
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REG_PCI_OR32(0xb0, 1 << 0), /* BDSM */
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REG_PCI_OR32(0xb4, 1 << 0), /* BGSM */
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REG_PCI_OR32(0xb8, 1 << 0), /* TSEGMB */
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REG_PCI_OR32(0xbc, 1 << 0), /* TOLUD */
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REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5500, 1 << 0), /* PAVP */
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REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31), /* SA PM */
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REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6020, 1 << 0), /* UMA GFX */
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REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x63fc, 1 << 0), /* VTDTRK */
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REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6800, 1 << 31),
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REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7000, 1 << 31),
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REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x77fc, 1 << 0),
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REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x50fc, 0x8f),
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REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7ffc, 1 << 0),
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REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5880, 1 << 5),
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REG_MMIO_WRITE8(MCH_BASE_ADDRESS + 0x50fc, 0x8f), /* MC */
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REG_SCRIPT_END
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};
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const struct reg_script pch_finalize_script[] = {
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/* Set SPI opcode menu */
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REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_PREOP,
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SPI_OPPREFIX),
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REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_OPTYPE,
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SPI_OPTYPE),
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET +
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SPIBAR_OPMENU_LOWER, SPI_OPMENU_LOWER),
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET +
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SPIBAR_OPMENU_UPPER, SPI_OPMENU_UPPER),
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/* Lock SPIBAR */
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REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS,
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SPIBAR_HSFS_FLOCKDN),
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/* TC Lockdown */
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REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)),
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/* BIOS Interface Lockdown */
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REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 0)),
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/* Function Disable SUS Well Lockdown */
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REG_MMIO_OR8(RCBA_BASE_ADDRESS + FDSW, (1 << 7)),
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/* Global SMI Lock */
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REG_PCI_OR16(GEN_PMCON_1, SMI_LOCK),
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/* GEN_PMCON Lock */
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REG_PCI_OR8(GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK),
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/* PMSYNC */
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REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)),
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REG_SCRIPT_END
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};
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static void broadwell_finalize(void *unused)
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{
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printk(BIOS_DEBUG, "Finalizing chipset.\n");
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reg_script_run_on_dev(SA_DEV_ROOT, system_agent_finalize_script);
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reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script);
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/* Lock */
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RCBA32_OR(0x3a6c, 0x00000001);
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/* Read+Write the following registers */
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MCHBAR32(0x6030) = MCHBAR32(0x6030);
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MCHBAR32(0x6034) = MCHBAR32(0x6034);
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MCHBAR32(0x6008) = MCHBAR32(0x6008);
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RCBA32(0x21a4) = RCBA32(0x21a4);
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/* Re-init SPI after lockdown */
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spi_init();
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printk(BIOS_DEBUG, "Finalizing SMM.\n");
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outb(APM_CNT_FINALIZE, APM_CNT);
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/* Indicate finalize step with post code */
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post_code(POST_OS_BOOT);
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}
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BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, broadwell_finalize, NULL);
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, broadwell_finalize, NULL);
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